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@ -0,0 +1,579 @@
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From fbfab1ab065879370541caf0e514987368eb41b2 Mon Sep 17 00:00:00 2001
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From: Abhishek Sahu <absahu@codeaurora.org>
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Date: Mon, 12 Mar 2018 18:45:01 +0530
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Subject: [PATCH 12/13] i2c: qup: reorganization of driver code to remove
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polling for qup v1
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Following are the major issues in current driver code
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1. The current driver simply assumes the transfer completion
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whenever its gets any non-error interrupts and then simply do the
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polling of available/free bytes in FIFO.
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2. The block mode is not working properly since no handling in
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being done for OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ.
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Because of above, i2c v1 transfers of size greater than 32 are failing
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with following error message
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i2c_qup 78b6000.i2c: timeout for fifo out full
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To make block mode working properly and move to use the interrupts
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instead of polling, major code reorganization is required. Following
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are the major changes done in this patch
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1. Remove the polling of TX FIFO free space and RX FIFO available
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bytes and move to interrupts completely. QUP has QUP_MX_OUTPUT_DONE,
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QUP_MX_INPUT_DONE, OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ
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interrupts to handle FIFO’s properly so check all these interrupts.
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2. During write, For FIFO mode, TX FIFO can be directly written
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without checking for FIFO space. For block mode, the QUP will generate
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OUT_BLOCK_WRITE_REQ interrupt whenever it has block size of available
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space.
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3. During read, both TX and RX FIFO will be used. TX will be used
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for writing tags and RX will be used for receiving the data. In QUP,
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TX and RX can operate in separate mode so configure modes accordingly.
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4. For read FIFO mode, wait for QUP_MX_INPUT_DONE interrupt which
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will be generated after all the bytes have been copied in RX FIFO. For
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read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts
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whenever it has block size of available data.
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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Reviewed-by: Sricharan R <sricharan@codeaurora.org>
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Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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---
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drivers/i2c/busses/i2c-qup.c | 366 +++++++++++++++++++++--------------
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1 file changed, 223 insertions(+), 143 deletions(-)
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--- a/drivers/i2c/busses/i2c-qup.c
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+++ b/drivers/i2c/busses/i2c-qup.c
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@@ -64,8 +64,11 @@
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#define QUP_IN_SVC_FLAG BIT(9)
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#define QUP_MX_OUTPUT_DONE BIT(10)
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#define QUP_MX_INPUT_DONE BIT(11)
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+#define OUT_BLOCK_WRITE_REQ BIT(12)
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+#define IN_BLOCK_READ_REQ BIT(13)
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/* I2C mini core related values */
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+#define QUP_NO_INPUT BIT(7)
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#define QUP_CLOCK_AUTO_GATE BIT(13)
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#define I2C_MINI_CORE (2 << 8)
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#define I2C_N_VAL 15
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@@ -137,13 +140,36 @@
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#define DEFAULT_CLK_FREQ 100000
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#define DEFAULT_SRC_CLK 20000000
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+/*
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+ * count: no of blocks
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+ * pos: current block number
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+ * tx_tag_len: tx tag length for current block
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+ * rx_tag_len: rx tag length for current block
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+ * data_len: remaining data length for current message
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+ * total_tx_len: total tx length including tag bytes for current QUP transfer
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+ * total_rx_len: total rx length including tag bytes for current QUP transfer
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+ * tx_fifo_free: number of free bytes in current QUP block write.
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+ * fifo_available: number of available bytes in RX FIFO for current
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+ * QUP block read
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+ * rx_bytes_read: if all the bytes have been read from rx FIFO.
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+ * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
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+ * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
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+ * tags: contains tx tag bytes for current QUP transfer
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+ */
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struct qup_i2c_block {
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- int count;
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- int pos;
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- int tx_tag_len;
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- int rx_tag_len;
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- int data_len;
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- u8 tags[6];
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+ int count;
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+ int pos;
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+ int tx_tag_len;
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+ int rx_tag_len;
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+ int data_len;
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+ int total_tx_len;
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+ int total_rx_len;
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+ int tx_fifo_free;
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+ int fifo_available;
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+ bool rx_bytes_read;
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+ bool is_tx_blk_mode;
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+ bool is_rx_blk_mode;
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+ u8 tags[6];
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};
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struct qup_i2c_tag {
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@@ -186,6 +212,7 @@ struct qup_i2c_dev {
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/* To check if this is the last msg */
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bool is_last;
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+ bool is_qup_v1;
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/* To configure when bus is in run state */
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int config_run;
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@@ -202,11 +229,18 @@ struct qup_i2c_dev {
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struct qup_i2c_bam btx;
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struct completion xfer;
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+ /* function to write data in tx fifo */
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+ void (*write_tx_fifo)(struct qup_i2c_dev *qup);
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+ /* function to read data from rx fifo */
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+ void (*read_rx_fifo)(struct qup_i2c_dev *qup);
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+ /* function to write tags in tx fifo for i2c read transfer */
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+ void (*write_rx_tags)(struct qup_i2c_dev *qup);
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};
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static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
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{
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struct qup_i2c_dev *qup = dev;
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+ struct qup_i2c_block *blk = &qup->blk;
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u32 bus_err;
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u32 qup_err;
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u32 opflags;
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@@ -253,12 +287,48 @@ static irqreturn_t qup_i2c_interrupt(int
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goto done;
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}
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- if (opflags & QUP_IN_SVC_FLAG)
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- writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
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+ if (!qup->is_qup_v1)
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+ goto done;
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- if (opflags & QUP_OUT_SVC_FLAG)
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+ if (opflags & QUP_OUT_SVC_FLAG) {
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writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
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+ if (opflags & OUT_BLOCK_WRITE_REQ) {
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+ blk->tx_fifo_free += qup->out_blk_sz;
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+ if (qup->msg->flags & I2C_M_RD)
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+ qup->write_rx_tags(qup);
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+ else
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+ qup->write_tx_fifo(qup);
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+ }
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+ }
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+
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+ if (opflags & QUP_IN_SVC_FLAG) {
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+ writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
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+
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+ if (!blk->is_rx_blk_mode) {
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+ blk->fifo_available += qup->in_fifo_sz;
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+ qup->read_rx_fifo(qup);
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+ } else if (opflags & IN_BLOCK_READ_REQ) {
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+ blk->fifo_available += qup->in_blk_sz;
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+ qup->read_rx_fifo(qup);
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+ }
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+ }
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+
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+ if (qup->msg->flags & I2C_M_RD) {
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+ if (!blk->rx_bytes_read)
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+ return IRQ_HANDLED;
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+ } else {
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+ /*
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+ * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked
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+ * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags
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+ * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason
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+ * of interrupt for write message in FIFO mode is
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+ * QUP_MAX_OUTPUT_DONE_FLAG condition.
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+ */
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+ if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE))
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+ return IRQ_HANDLED;
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+ }
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+
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done:
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qup->qup_err = qup_err;
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qup->bus_err = bus_err;
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@@ -324,6 +394,28 @@ static int qup_i2c_change_state(struct q
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return 0;
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}
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+/* Check if I2C bus returns to IDLE state */
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+static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len)
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+{
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+ unsigned long timeout;
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+ u32 status;
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+ int ret = 0;
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+
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+ timeout = jiffies + len * 4;
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+ for (;;) {
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+ status = readl(qup->base + QUP_I2C_STATUS);
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+ if (!(status & I2C_STATUS_BUS_ACTIVE))
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+ break;
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+
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+ if (time_after(jiffies, timeout))
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+ ret = -ETIMEDOUT;
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+
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+ usleep_range(len, len * 2);
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+ }
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+
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+ return ret;
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+}
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+
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/**
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* qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
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* @qup: The qup_i2c_dev device
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@@ -394,23 +486,6 @@ static void qup_i2c_set_write_mode_v2(st
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}
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}
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-static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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-{
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- /* Number of entries to shift out, including the start */
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- int total = msg->len + 1;
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-
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- if (total < qup->out_fifo_sz) {
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- /* FIFO mode */
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- writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
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- writel(total, qup->base + QUP_MX_WRITE_CNT);
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- } else {
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- /* BLOCK mode (transfer data on chunks) */
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- writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
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- qup->base + QUP_IO_MODE);
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- writel(total, qup->base + QUP_MX_OUTPUT_CNT);
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- }
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-}
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-
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static int check_for_fifo_space(struct qup_i2c_dev *qup)
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{
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int ret;
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@@ -443,28 +518,25 @@ out:
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return ret;
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}
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-static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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+static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup)
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{
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+ struct qup_i2c_block *blk = &qup->blk;
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+ struct i2c_msg *msg = qup->msg;
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u32 addr = msg->addr << 1;
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u32 qup_tag;
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int idx;
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u32 val;
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- int ret = 0;
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if (qup->pos == 0) {
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val = QUP_TAG_START | addr;
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idx = 1;
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+ blk->tx_fifo_free--;
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} else {
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val = 0;
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idx = 0;
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}
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- while (qup->pos < msg->len) {
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- /* Check that there's space in the FIFO for our pair */
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- ret = check_for_fifo_space(qup);
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- if (ret)
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- return ret;
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-
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+ while (blk->tx_fifo_free && qup->pos < msg->len) {
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if (qup->pos == msg->len - 1)
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qup_tag = QUP_TAG_STOP;
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else
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@@ -481,11 +553,8 @@ static int qup_i2c_issue_write(struct qu
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qup->pos++;
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idx++;
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+ blk->tx_fifo_free--;
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}
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-
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- ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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-
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- return ret;
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}
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static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
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@@ -1006,64 +1075,6 @@ err:
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return ret;
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}
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-static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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-{
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- int ret;
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-
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- qup->msg = msg;
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- qup->pos = 0;
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-
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- enable_irq(qup->irq);
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-
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- qup_i2c_set_write_mode(qup, msg);
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-
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- ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
|
|
|
|
- if (ret)
|
|
|
|
|
- goto err;
|
|
|
|
|
-
|
|
|
|
|
- writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
|
|
|
|
|
-
|
|
|
|
|
- do {
|
|
|
|
|
- ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
|
|
|
|
|
- if (ret)
|
|
|
|
|
- goto err;
|
|
|
|
|
-
|
|
|
|
|
- ret = qup_i2c_issue_write(qup, msg);
|
|
|
|
|
- if (ret)
|
|
|
|
|
- goto err;
|
|
|
|
|
-
|
|
|
|
|
- ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
|
|
|
|
- if (ret)
|
|
|
|
|
- goto err;
|
|
|
|
|
-
|
|
|
|
|
- ret = qup_i2c_wait_for_complete(qup, msg);
|
|
|
|
|
- if (ret)
|
|
|
|
|
- goto err;
|
|
|
|
|
- } while (qup->pos < msg->len);
|
|
|
|
|
-
|
|
|
|
|
- /* Wait for the outstanding data in the fifo to drain */
|
|
|
|
|
- ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
|
|
|
|
|
-err:
|
|
|
|
|
- disable_irq(qup->irq);
|
|
|
|
|
- qup->msg = NULL;
|
|
|
|
|
-
|
|
|
|
|
- return ret;
|
|
|
|
|
-}
|
|
|
|
|
-
|
|
|
|
|
-static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
|
|
|
|
|
-{
|
|
|
|
|
- if (len < qup->in_fifo_sz) {
|
|
|
|
|
- /* FIFO mode */
|
|
|
|
|
- writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
|
|
|
|
|
- writel(len, qup->base + QUP_MX_READ_CNT);
|
|
|
|
|
- } else {
|
|
|
|
|
- /* BLOCK mode (transfer data on chunks) */
|
|
|
|
|
- writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
|
|
|
|
|
- qup->base + QUP_IO_MODE);
|
|
|
|
|
- writel(len, qup->base + QUP_MX_INPUT_CNT);
|
|
|
|
|
- }
|
|
|
|
|
-}
|
|
|
|
|
-
|
|
|
|
|
static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev *qup, int len)
|
|
|
|
|
{
|
|
|
|
|
int tx_len = qup->blk.tx_tag_len;
|
|
|
|
|
@@ -1086,44 +1097,27 @@ static void qup_i2c_set_read_mode_v2(str
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
-static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
|
|
-{
|
|
|
|
|
- u32 addr, len, val;
|
|
|
|
|
-
|
|
|
|
|
- addr = i2c_8bit_addr_from_msg(msg);
|
|
|
|
|
-
|
|
|
|
|
- /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
|
|
|
|
|
- len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
|
|
|
|
|
-
|
|
|
|
|
- val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
|
|
|
|
|
- writel(val, qup->base + QUP_OUT_FIFO_BASE);
|
|
|
|
|
-}
|
|
|
|
|
-
|
|
|
|
|
-
|
|
|
|
|
-static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
|
|
+static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup)
|
|
|
|
|
{
|
|
|
|
|
+ struct qup_i2c_block *blk = &qup->blk;
|
|
|
|
|
+ struct i2c_msg *msg = qup->msg;
|
|
|
|
|
u32 val = 0;
|
|
|
|
|
- int idx;
|
|
|
|
|
- int ret = 0;
|
|
|
|
|
+ int idx = 0;
|
|
|
|
|
|
|
|
|
|
- for (idx = 0; qup->pos < msg->len; idx++) {
|
|
|
|
|
+ while (blk->fifo_available && qup->pos < msg->len) {
|
|
|
|
|
if ((idx & 1) == 0) {
|
|
|
|
|
- /* Check that FIFO have data */
|
|
|
|
|
- ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
|
|
|
|
|
- SET_BIT, 4 * ONE_BYTE);
|
|
|
|
|
- if (ret)
|
|
|
|
|
- return ret;
|
|
|
|
|
-
|
|
|
|
|
/* Reading 2 words at time */
|
|
|
|
|
val = readl(qup->base + QUP_IN_FIFO_BASE);
|
|
|
|
|
-
|
|
|
|
|
msg->buf[qup->pos++] = val & 0xFF;
|
|
|
|
|
} else {
|
|
|
|
|
msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
|
|
|
|
|
}
|
|
|
|
|
+ idx++;
|
|
|
|
|
+ blk->fifo_available--;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
- return ret;
|
|
|
|
|
+ if (qup->pos == msg->len)
|
|
|
|
|
+ blk->rx_bytes_read = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int qup_i2c_read_fifo_v2(struct qup_i2c_dev *qup,
|
|
|
|
|
@@ -1224,49 +1218,130 @@ err:
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
-static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
|
|
+static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup)
|
|
|
|
|
{
|
|
|
|
|
- int ret;
|
|
|
|
|
+ struct i2c_msg *msg = qup->msg;
|
|
|
|
|
+ u32 addr, len, val;
|
|
|
|
|
|
|
|
|
|
- qup->msg = msg;
|
|
|
|
|
- qup->pos = 0;
|
|
|
|
|
+ addr = i2c_8bit_addr_from_msg(msg);
|
|
|
|
|
|
|
|
|
|
- enable_irq(qup->irq);
|
|
|
|
|
- qup_i2c_set_read_mode(qup, msg->len);
|
|
|
|
|
+ /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
|
|
|
|
|
+ len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
|
|
|
|
|
+
|
|
|
|
|
+ val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
|
|
|
|
|
+ writel(val, qup->base + QUP_OUT_FIFO_BASE);
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)
|
|
|
|
|
+{
|
|
|
|
|
+ struct qup_i2c_block *blk = &qup->blk;
|
|
|
|
|
+ u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
|
|
|
|
|
+ u32 io_mode = QUP_REPACK_EN;
|
|
|
|
|
+
|
|
|
|
|
+ blk->is_tx_blk_mode =
|
|
|
|
|
+ blk->total_tx_len > qup->out_fifo_sz ? true : false;
|
|
|
|
|
+ blk->is_rx_blk_mode =
|
|
|
|
|
+ blk->total_rx_len > qup->in_fifo_sz ? true : false;
|
|
|
|
|
+
|
|
|
|
|
+ if (blk->is_tx_blk_mode) {
|
|
|
|
|
+ io_mode |= QUP_OUTPUT_BLK_MODE;
|
|
|
|
|
+ writel(0, qup->base + QUP_MX_WRITE_CNT);
|
|
|
|
|
+ writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
|
|
|
|
|
+ } else {
|
|
|
|
|
+ writel(0, qup->base + QUP_MX_OUTPUT_CNT);
|
|
|
|
|
+ writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ if (blk->total_rx_len) {
|
|
|
|
|
+ if (blk->is_rx_blk_mode) {
|
|
|
|
|
+ io_mode |= QUP_INPUT_BLK_MODE;
|
|
|
|
|
+ writel(0, qup->base + QUP_MX_READ_CNT);
|
|
|
|
|
+ writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
|
|
|
|
|
+ } else {
|
|
|
|
|
+ writel(0, qup->base + QUP_MX_INPUT_CNT);
|
|
|
|
|
+ writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
|
|
|
|
|
+ }
|
|
|
|
|
+ } else {
|
|
|
|
|
+ qup_config |= QUP_NO_INPUT;
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ writel(qup_config, qup->base + QUP_CONFIG);
|
|
|
|
|
+ writel(io_mode, qup->base + QUP_IO_MODE);
|
|
|
|
|
+}
|
|
|
|
|
|
|
|
|
|
+static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk)
|
|
|
|
|
+{
|
|
|
|
|
+ blk->tx_fifo_free = 0;
|
|
|
|
|
+ blk->fifo_available = 0;
|
|
|
|
|
+ blk->rx_bytes_read = false;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx)
|
|
|
|
|
+{
|
|
|
|
|
+ struct qup_i2c_block *blk = &qup->blk;
|
|
|
|
|
+ int ret;
|
|
|
|
|
+
|
|
|
|
|
+ qup_i2c_clear_blk_v1(blk);
|
|
|
|
|
+ qup_i2c_conf_v1(qup);
|
|
|
|
|
ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
|
|
|
|
if (ret)
|
|
|
|
|
- goto err;
|
|
|
|
|
+ return ret;
|
|
|
|
|
|
|
|
|
|
writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
|
|
|
|
|
|
|
|
|
|
ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
|
|
|
|
|
if (ret)
|
|
|
|
|
- goto err;
|
|
|
|
|
+ return ret;
|
|
|
|
|
+
|
|
|
|
|
+ reinit_completion(&qup->xfer);
|
|
|
|
|
+ enable_irq(qup->irq);
|
|
|
|
|
+ if (!blk->is_tx_blk_mode) {
|
|
|
|
|
+ blk->tx_fifo_free = qup->out_fifo_sz;
|
|
|
|
|
|
|
|
|
|
- qup_i2c_issue_read(qup, msg);
|
|
|
|
|
+ if (is_rx)
|
|
|
|
|
+ qup_i2c_write_rx_tags_v1(qup);
|
|
|
|
|
+ else
|
|
|
|
|
+ qup_i2c_write_tx_fifo_v1(qup);
|
|
|
|
|
+ }
|
|
|
|
|
|
|
|
|
|
ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
|
|
- do {
|
|
|
|
|
- ret = qup_i2c_wait_for_complete(qup, msg);
|
|
|
|
|
- if (ret)
|
|
|
|
|
- goto err;
|
|
|
|
|
+ ret = qup_i2c_wait_for_complete(qup, qup->msg);
|
|
|
|
|
+ if (ret)
|
|
|
|
|
+ goto err;
|
|
|
|
|
|
|
|
|
|
- ret = qup_i2c_read_fifo(qup, msg);
|
|
|
|
|
- if (ret)
|
|
|
|
|
- goto err;
|
|
|
|
|
- } while (qup->pos < msg->len);
|
|
|
|
|
+ ret = qup_i2c_bus_active(qup, ONE_BYTE);
|
|
|
|
|
|
|
|
|
|
err:
|
|
|
|
|
disable_irq(qup->irq);
|
|
|
|
|
- qup->msg = NULL;
|
|
|
|
|
-
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
+static int qup_i2c_write_one(struct qup_i2c_dev *qup)
|
|
|
|
|
+{
|
|
|
|
|
+ struct i2c_msg *msg = qup->msg;
|
|
|
|
|
+ struct qup_i2c_block *blk = &qup->blk;
|
|
|
|
|
+
|
|
|
|
|
+ qup->pos = 0;
|
|
|
|
|
+ blk->total_tx_len = msg->len + 1;
|
|
|
|
|
+ blk->total_rx_len = 0;
|
|
|
|
|
+
|
|
|
|
|
+ return qup_i2c_conf_xfer_v1(qup, false);
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static int qup_i2c_read_one(struct qup_i2c_dev *qup)
|
|
|
|
|
+{
|
|
|
|
|
+ struct qup_i2c_block *blk = &qup->blk;
|
|
|
|
|
+
|
|
|
|
|
+ qup->pos = 0;
|
|
|
|
|
+ blk->total_tx_len = 2;
|
|
|
|
|
+ blk->total_rx_len = qup->msg->len;
|
|
|
|
|
+
|
|
|
|
|
+ return qup_i2c_conf_xfer_v1(qup, true);
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
static int qup_i2c_xfer(struct i2c_adapter *adap,
|
|
|
|
|
struct i2c_msg msgs[],
|
|
|
|
|
int num)
|
|
|
|
|
@@ -1305,10 +1380,11 @@ static int qup_i2c_xfer(struct i2c_adapt
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
+ qup->msg = &msgs[idx];
|
|
|
|
|
if (msgs[idx].flags & I2C_M_RD)
|
|
|
|
|
- ret = qup_i2c_read_one(qup, &msgs[idx]);
|
|
|
|
|
+ ret = qup_i2c_read_one(qup);
|
|
|
|
|
else
|
|
|
|
|
- ret = qup_i2c_write_one(qup, &msgs[idx]);
|
|
|
|
|
+ ret = qup_i2c_write_one(qup);
|
|
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
|
break;
|
|
|
|
|
@@ -1487,6 +1563,10 @@ static int qup_i2c_probe(struct platform
|
|
|
|
|
if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
|
|
|
|
|
qup->adap.algo = &qup_i2c_algo;
|
|
|
|
|
qup->adap.quirks = &qup_i2c_quirks;
|
|
|
|
|
+ qup->is_qup_v1 = true;
|
|
|
|
|
+ qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
|
|
|
|
|
+ qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
|
|
|
|
|
+ qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
|
|
|
|
|
} else {
|
|
|
|
|
qup->adap.algo = &qup_i2c_algo_v2;
|
|
|
|
|
ret = qup_i2c_req_dma(qup);
|
Piotr Dymacz
5 years ago