ar71xx: add support for Gainstrong MiniBox V3.2
Adds MiniBox V3.2 ar71xx target (QCA99531 + QCA9887) Info: http://oolite.cn/minibox-v3-2-qca9531-qca9887-module-pin-specification.html Reference patch: http://oolite.cn/wp-content/uploads/2017/09/minibox_v3_cc15.05_20160325.patch Installation: Upload firmware to uboot via HTTP at 192.168.1.1 (press button for 5 seconds) Signed-off-by: Pau Escrich <p4u@dabax.net> Signed-off-by: Daniel Golle <daniel@makrotopia.org> (daniel@makrotopia.org: rebased and fixed conflicts, fixed LED name, added ath10k eeprom)v19.07.3_mercusys_ac12_duma
Pau Escrich
6 years ago
committed by
Daniel Golle
parent
c6a1bcac16
commit
15f16bf05b
@ -0,0 +1,121 @@
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/*
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* Atheros GS_MINIBOX_V3.2 reference board support
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*
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* Copyright (c) 2018 OpenWRT.org
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* Copyright (c) 2013 The Linux Foundation. All rights reserved.
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* Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <linux/ar8216_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-eth.h"
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#include "dev-ap9x-pci.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#include "pci.h"
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#define GS_MINIBOX_V3_GPIO_LED_STATUS 14
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#define GS_MINIBOX_V3_GPIO_BTN_RST 17
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#define GS_MINIBOX_V3_KEYS_POLL_INTERVAL 20 /* msecs */
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#define GS_MINIBOX_V3_KEYS_DEBOUNCE_INTERVAL (3 * GS_MINIBOX_V3_KEYS_POLL_INTERVAL)
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#define GS_MINIBOX_V3_MAC0_OFFSET 0
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#define GS_MINIBOX_V3_MAC1_OFFSET 6
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#define GS_MINIBOX_V3_WMAC_CALDATA_OFFSET 0x1000
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static const char *gs_minibox_v3_part_probes[] = {
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"tp-link",
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NULL,
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};
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static struct flash_platform_data gs_minibox_v3_flash_data = {
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.part_probes = gs_minibox_v3_part_probes,
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};
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static struct gpio_led gs_minibox_v3_leds_gpio[] __initdata = {
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{
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.name = "minibox_v3.2:green:system",
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.gpio = GS_MINIBOX_V3_GPIO_LED_STATUS,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button gs_minibox_v3_gpio_keys[] __initdata = {
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{
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.desc = "reset button",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = GS_MINIBOX_V3_KEYS_DEBOUNCE_INTERVAL,
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.gpio = GS_MINIBOX_V3_GPIO_BTN_RST,
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.active_low = 1,
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},
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};
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static void __init gs_minibox_v3_gpio_led_setup(void)
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{
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ath79_register_leds_gpio(-1, ARRAY_SIZE(gs_minibox_v3_leds_gpio),
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gs_minibox_v3_leds_gpio);
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ath79_register_gpio_keys_polled(-1, GS_MINIBOX_V3_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(gs_minibox_v3_gpio_keys),
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gs_minibox_v3_gpio_keys);
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}
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static void __init gs_minibox_v3_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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ath79_register_m25p80(&gs_minibox_v3_flash_data);
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gs_minibox_v3_gpio_led_setup();
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ath79_register_usb();
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ath79_register_wmac(art + GS_MINIBOX_V3_WMAC_CALDATA_OFFSET, NULL);
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ath79_register_mdio(0, 0x0);
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ath79_register_mdio(1, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr, art + GS_MINIBOX_V3_MAC0_OFFSET, 0);
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ath79_init_mac(ath79_eth1_data.mac_addr, art + GS_MINIBOX_V3_MAC1_OFFSET, 0);
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/* WAN port */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.speed = SPEED_100;
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ath79_eth0_data.duplex = DUPLEX_FULL;
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ath79_eth0_data.phy_mask = BIT(4);
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ath79_register_eth(0);
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/* LAN ports */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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ath79_eth1_data.speed = SPEED_1000;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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ath79_switch_data.phy_poll_mask |= BIT(4);
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ath79_switch_data.phy4_mii_en = 1;
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ath79_register_eth(1);
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ath79_register_pci();
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}
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MIPS_MACHINE(ATH79_MACH_GS_MINIBOX_V32, "MINIBOX-V3.2", "Minibox V3.2",
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gs_minibox_v3_setup);
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