uboot-sunxi: update to version 2017.07
The deleted patches are already integrated in the upstream U-Boot version. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>v19.07.3_mercusys_ac12_duma
Hauke Mehrtens
7 years ago
parent
ea9fab904b
commit
1422d4435b
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,38 +0,0 @@
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From 730d2f3a41c5ccae71b5008fffdf697d143be68c Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Wed, 16 Mar 2016 20:44:51 +0100
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Subject: [PATCH] sunxi: Fix clock_twi_onoff for sun6i
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The clock_sun6i.c implementation was not deasserting the reset for
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the regular i2c controllers, this commit fixes this.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Ian Campbell <ijc@hellion.org.uk>
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---
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arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 11 ++++++++---
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1 file changed, 8 insertions(+), 3 deletions(-)
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--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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@@ -100,13 +100,18 @@ int clock_twi_onoff(int port, int state)
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return 0;
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}
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- /* set the apb clock gate for twi */
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- if (state)
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+ /* set the apb clock gate and reset for twi */
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+ if (state) {
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setbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
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- else
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+ setbits_le32(&ccm->apb2_reset_cfg,
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+ 1 << (APB2_RESET_TWI_SHIFT + port));
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+ } else {
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+ clrbits_le32(&ccm->apb2_reset_cfg,
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+ 1 << (APB2_RESET_TWI_SHIFT + port));
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clrbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
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+ }
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return 0;
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}
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@ -1,24 +0,0 @@
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From 1eae8f66ff749409eb96e2f3f3387c56232d0b8a Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Wed, 16 Mar 2016 13:46:22 +0100
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Subject: [PATCH] sunxi: Enable realtek phy support
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Enable building of drivers/net/phy/realtek.c so that realtek phys
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get properly initialized.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Ian Campbell <ijc@hellion.org.uk>
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---
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include/configs/sunxi-common.h | 1 +
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1 file changed, 1 insertion(+)
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--- a/include/configs/sunxi-common.h
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+++ b/include/configs/sunxi-common.h
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@@ -314,6 +314,7 @@ extern int soft_i2c_gpio_scl;
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#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
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#define CONFIG_PHY_ADDR 1
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#define CONFIG_MII /* MII PHY management */
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+#define CONFIG_PHY_REALTEK
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#endif
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#ifdef CONFIG_USB_EHCI_HCD
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@ -1,127 +0,0 @@
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From fc8991c61c393ce6a9d3dfc97cb56dbbd9e8cbba Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Thu, 17 Mar 2016 13:53:03 +0100
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Subject: [PATCH] sunxi: Fix gmac not working due to cpu_eth_init no longer
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being called
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cpu_eth_init is no longer called for dm enabled eth drivers, this
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was causing the sunxi gmac eth controller to no longer work in u-boot.
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This commit fixes this by calling the clock, reset and pinmux setup
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function from s_init() and enabling the phy power pin (if any) from
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board_init().
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The enabling of phy power cannot be done from s_init because it uses dm
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and dm is not ready yet at this point.
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Note that the mdelay is dropped as the phy gets enabled much earlier
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now, so it is no longer needed.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Tested-by: Karsten Merker <merker@debian.org>
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Tested-by: Michael Haas <haas@computerlinguist.org>
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---
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arch/arm/cpu/armv7/sunxi/board.c | 28 +---------------------------
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arch/arm/include/asm/arch-sunxi/sys_proto.h | 6 +++++-
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board/sunxi/board.c | 5 +++++
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board/sunxi/gmac.c | 14 +-------------
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4 files changed, 12 insertions(+), 41 deletions(-)
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--- a/arch/arm/cpu/armv7/sunxi/board.c
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+++ b/arch/arm/cpu/armv7/sunxi/board.c
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@@ -136,6 +136,7 @@ void s_init(void)
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timer_init();
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gpio_init();
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i2c_init_board();
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+ eth_init_board();
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}
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#ifdef CONFIG_SPL_BUILD
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@@ -243,30 +244,3 @@ void enable_caches(void)
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dcache_enable();
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}
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#endif
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-
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-#ifdef CONFIG_CMD_NET
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-/*
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- * Initializes on-chip ethernet controllers.
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- * to override, implement board_eth_init()
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- */
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-int cpu_eth_init(bd_t *bis)
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-{
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- __maybe_unused int rc;
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-
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-#ifdef CONFIG_MACPWR
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- gpio_request(CONFIG_MACPWR, "macpwr");
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- gpio_direction_output(CONFIG_MACPWR, 1);
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- mdelay(200);
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-#endif
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-
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-#ifdef CONFIG_SUNXI_GMAC
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- rc = sunxi_gmac_initialize(bis);
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- if (rc < 0) {
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- printf("sunxi: failed to initialize gmac\n");
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- return rc;
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- }
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-#endif
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-
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- return 0;
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-}
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-#endif
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--- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
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+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
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@@ -24,6 +24,10 @@ void sdelay(unsigned long);
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void return_to_fel(uint32_t lr, uint32_t sp);
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/* Board / SoC level designware gmac init */
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-int sunxi_gmac_initialize(bd_t *bis);
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+#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUNXI_GMAC
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+void eth_init_board(void);
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+#else
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+static inline void eth_init_board(void) {}
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+#endif
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#endif
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--- a/board/sunxi/board.c
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+++ b/board/sunxi/board.c
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@@ -90,6 +90,11 @@ int board_init(void)
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if (ret)
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return ret;
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+#ifdef CONFIG_MACPWR
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+ gpio_request(CONFIG_MACPWR, "macpwr");
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+ gpio_direction_output(CONFIG_MACPWR, 1);
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+#endif
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+
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/* Uses dm gpio code so do this here and not in i2c_init_board() */
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return soft_i2c_board_init();
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}
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--- a/board/sunxi/gmac.c
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+++ b/board/sunxi/gmac.c
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@@ -6,7 +6,7 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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-int sunxi_gmac_initialize(bd_t *bis)
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+void eth_init_board(void)
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{
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int pin;
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struct sunxi_ccm_reg *const ccm =
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@@ -79,16 +79,4 @@ int sunxi_gmac_initialize(bd_t *bis)
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for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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#endif
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-
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-#ifdef CONFIG_DM_ETH
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- return 0;
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-#else
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-# ifdef CONFIG_RGMII
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- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
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-# elif defined CONFIG_GMII
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- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
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-# else
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- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
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-# endif
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-#endif
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}
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@ -1,78 +0,0 @@
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From 948603d4d637a0e04a3214253b911cfc4ed11220 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Mon, 21 Mar 2016 14:44:35 +0100
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Subject: [PATCH] sunxi: Fix 2nd usb controller on sun4i/sun7i no longer
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working
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The 2nd usb controller on sun4i/sun7i has its base address 0x8000
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bytes from the 1st one, rather then 0x1000. Also the ahb clk gates
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are interleaved with the ohci clk-gates introducing a hole between
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the clks for usb1 and usb2.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Ian Campbell <ijc@hellion.org.uk>
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---
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drivers/usb/host/ehci-sunxi.c | 13 +++++++++++--
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drivers/usb/host/ohci-sunxi.c | 15 ++++++++++++---
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2 files changed, 23 insertions(+), 5 deletions(-)
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--- a/drivers/usb/host/ehci-sunxi.c
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+++ b/drivers/usb/host/ehci-sunxi.c
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@@ -17,6 +17,14 @@
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#include <dm.h>
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#include "ehci.h"
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+#ifdef CONFIG_SUNXI_GEN_SUN4I
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+#define BASE_DIST 0x8000
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+#define AHB_CLK_DIST 2
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+#else
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+#define BASE_DIST 0x1000
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+#define AHB_CLK_DIST 1
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+#endif
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+
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struct ehci_sunxi_priv {
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struct ehci_ctrl ehci;
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int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
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@@ -39,8 +47,9 @@ static int ehci_usb_probe(struct udevice
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#ifdef CONFIG_MACH_SUN8I_H3
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priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
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#endif
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- priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
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- priv->ahb_gate_mask <<= priv->phy_index - 1;
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+ priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
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+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
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+ priv->phy_index++; /* Non otg phys start at 1 */
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setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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--- a/drivers/usb/host/ohci-sunxi.c
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+++ b/drivers/usb/host/ohci-sunxi.c
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@@ -17,6 +17,14 @@
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#include <usb.h>
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#include "ohci.h"
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+#ifdef CONFIG_SUNXI_GEN_SUN4I
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+#define BASE_DIST 0x8000
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+#define AHB_CLK_DIST 2
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+#else
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+#define BASE_DIST 0x1000
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+#define AHB_CLK_DIST 1
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+#endif
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+
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struct ohci_sunxi_priv {
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ohci_t ohci;
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int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
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@@ -42,9 +50,10 @@ static int ohci_usb_probe(struct udevice
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priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
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#endif
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priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
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- priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
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- priv->ahb_gate_mask <<= priv->phy_index - 1;
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- priv->usb_gate_mask <<= priv->phy_index - 1;
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+ priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
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+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
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+ priv->usb_gate_mask <<= priv->phy_index;
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+ priv->phy_index++; /* Non otg phys start at 1 */
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setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
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setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);
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@ -1,31 +0,0 @@
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From 8f10b5c65611e6c15a113bf63289b6696452f90d Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Sun, 20 Mar 2016 14:17:10 +0100
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Subject: [PATCH] spl: Print from which mmc slot spl is trying to boot
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On some sunxi boards (and presumably also non sunxi boards) u-boot can
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be either loaded from a sdcard in a micro-sd slot, or from eMMC.
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Print which MMC spl tries to boot from, to help debugging.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Reviewed-by: Tom Rini <trini@konsulko.com>
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---
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common/spl/spl.c | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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--- a/common/spl/spl.c
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+++ b/common/spl/spl.c
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@@ -210,9 +210,9 @@ struct boot_device_name boot_name_table[
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{ BOOT_DEVICE_RAM, "RAM" },
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#endif
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#ifdef CONFIG_SPL_MMC_SUPPORT
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- { BOOT_DEVICE_MMC1, "MMC" },
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- { BOOT_DEVICE_MMC2, "MMC" },
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- { BOOT_DEVICE_MMC2_2, "MMC" },
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+ { BOOT_DEVICE_MMC1, "MMC1" },
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+ { BOOT_DEVICE_MMC2, "MMC2" },
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+ { BOOT_DEVICE_MMC2_2, "MMC2_2" },
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#endif
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#ifdef CONFIG_SPL_NAND_SUPPORT
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{ BOOT_DEVICE_NAND, "NAND" },
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@ -1,39 +0,0 @@
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From 60fa63012fcdc3c4ec1497bf5e358f0a90b40949 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Fri, 18 Mar 2016 08:42:01 +0100
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Subject: [PATCH] sunxi: Add support for USB vbus pin for USB3
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The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Ian Campbell <ijc@hellion.org.uk>
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---
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arch/arm/cpu/armv7/sunxi/usb_phy.c | 1 +
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board/sunxi/Kconfig | 6 ++++++
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2 files changed, 7 insertions(+)
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--- a/arch/arm/cpu/armv7/sunxi/usb_phy.c
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+++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c
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@@ -76,6 +76,7 @@ static int get_vbus_gpio(int index)
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case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
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case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
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case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
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+ case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
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}
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return -EINVAL;
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}
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--- a/board/sunxi/Kconfig
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+++ b/board/sunxi/Kconfig
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@@ -341,6 +341,12 @@ config USB2_VBUS_PIN
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---help---
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See USB1_VBUS_PIN help text.
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+config USB3_VBUS_PIN
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+ string "Vbus enable pin for usb3 (ehci2)"
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+ default ""
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+ ---help---
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+ See USB1_VBUS_PIN help text.
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+
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config I2C0_ENABLE
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bool "Enable I2C/TWI controller 0"
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default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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@ -1,31 +0,0 @@
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From ce0d0926758f631fdd655d438acd32d5935d43a4 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Fri, 18 Mar 2016 08:45:21 +0100
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Subject: [PATCH] sunxi: Specify USB vbus pins for orangepi boards
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This fixes the USB ports not working on the orangepi_plus and stops us
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from messing with gpio-s which we should not touch on the orangepi_pc.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Ian Campbell <ijc@hellion.org.uk>
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---
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configs/orangepi_pc_defconfig | 3 +++
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configs/orangepi_plus_defconfig | 1 +
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2 files changed, 4 insertions(+)
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--- a/configs/orangepi_pc_defconfig
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+++ b/configs/orangepi_pc_defconfig
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@@ -14,3 +14,6 @@ CONFIG_SPL=y
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CONFIG_CMD_GPIO=y
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CONFIG_SY8106A_POWER=y
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CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB1_VBUS_PIN=""
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+CONFIG_USB2_VBUS_PIN=""
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+CONFIG_USB3_VBUS_PIN=""
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--- a/configs/orangepi_plus_defconfig
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+++ b/configs/orangepi_plus_defconfig
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@@ -14,3 +14,4 @@ CONFIG_SPL=y
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CONFIG_CMD_GPIO=y
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CONFIG_SY8106A_POWER=y
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CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB1_VBUS_PIN="PG13"
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@ -1,33 +0,0 @@
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From 70fe24ed93fa90eb407d18a5fc9d9ad85ac9184c Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Wed, 27 Jan 2016 16:34:43 +0800
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Subject: [PATCH] sunxi: Support SID e-fuses on A83T and H3
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On the A83T and H3, the SID block is at a different address.
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Furthurmore, the e-fuses are at an offset of 0x200 within the
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hardware's address space.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Acked-by: Hans de Goede <hdegoede@redhat.com>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
|
||||
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
|
||||
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
|
||||
@@ -82,7 +82,14 @@
|
||||
#define SUNXI_AD_DA_BASE 0x01c22c00
|
||||
#define SUNXI_KEYPAD_BASE 0x01c23000
|
||||
#define SUNXI_TZPC_BASE 0x01c23400
|
||||
+
|
||||
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3)
|
||||
+/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
|
||||
+#define SUNXI_SID_BASE 0x01c14200
|
||||
+#else
|
||||
#define SUNXI_SID_BASE 0x01c23800
|
||||
+#endif
|
||||
+
|
||||
#define SUNXI_SJTAG_BASE 0x01c23c00
|
||||
|
||||
#define SUNXI_TP_BASE 0x01c25000
|
||||
@ -1,23 +0,0 @@
|
||||
From 2af25b747340c6c8f6a6b9e27632db577bf4da52 Mon Sep 17 00:00:00 2001
|
||||
From: Simon Glass <sjg@chromium.org>
|
||||
Date: Mon, 22 Feb 2016 22:55:46 -0700
|
||||
Subject: [PATCH] sunxi: Display the board model on start-up
|
||||
|
||||
It is useful to know which sunxi board you are booting. Display this on
|
||||
start-up to avoid confusion.
|
||||
|
||||
Signed-off-by: Simon Glass <sjg@chromium.org>
|
||||
---
|
||||
include/configs/sunxi-common.h | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/include/configs/sunxi-common.h
|
||||
+++ b/include/configs/sunxi-common.h
|
||||
@@ -174,6 +174,7 @@
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
|
||||
#define CONFIG_IDENT_STRING " Allwinner Technology"
|
||||
+#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
|
||||
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
|
||||
Loading…
Reference in New Issue