ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
Incorrect value causes clock inaccuracy as huge as 1/60. Signed-off-by: Dmitry Ivanov <dima@ubnt.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 47363v19.07.3_mercusys_ac12_duma
parent
a946367371
commit
0b296d3808
Loading…
Reference in New Issue