ar71xx: add support for the Airtight C-60
This patch adds support for the Airtight C-60.
SOC: Atheros AR9344 rev 2 (CPU:560.000MHz)
RAM: 128 MiB
NOR: MX25L3205D 4MiB
NAND: ST Micro NAND 32MiB 3,3V 8-bit
SW-NET: AR8327N (2 Ports)
WLAN1: Dual-Band AR9340 Rev:2 (built-in SoC)
WLAN2: Dual-Band AR9300 Rev:4 PCIe Chip
The switch is setup for an accesspoint:
LAN1: (gigabit) is the wan-port.
LAN2: (fast ethernet) is bridged with the br-lan.
Flashing Guide (via initramfs):
1. Connect a PC to the serial port of the C-60.
power up the C-60.
Enter u-boot command prompt:
#> nand erase
#> setenv bootcmd "bootm 0x9f060000"
#> saveenv
#> setenv ipaddr 192.168.1.1
#> setenv netmask 255.255.255.0
#> setenv serverip 192.168.1.100
#> setenv bootfile lede-ar71xx-nand-c-60-initramfs-kernel.bin
#> tftpboot
#> bootm
2. Wait for the C-60 to boot LEDE.
On the root prompt. Enter:
# ubiformat /dev/mtd4
# ubiattach -p /dev/mtd4
3. After that copy the sysupgrade.tar onto the router and run:
# sysupgrade sysupgrade.tar
to flash the image.
Special thanks to Chris Blake <chrisrblake93@gmail.com>. He provided
a C-60 unit and he helped with debugging the switch, LEDs and platfrom
support.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
v19.07.3_mercusys_ac12_duma
Christian Lamparter
8 years ago
committed by
John Crispin
parent
e9455c561d
commit
098f7156cc
@ -0,0 +1,200 @@
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/*
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* AirTight Networks C-60 board support
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*
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* Copyright (C) 2016 Christian Lamparter <chunkeey@googlemail.com>
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*
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* Based on AirTight Networks C-55 board support
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*
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* Copyright (C) 2014-2015 Chris Blake <chrisrblake93@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_device.h>
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#include <linux/platform/ar934x_nfc.h>
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#include <linux/ar8216_platform.h>
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#include <linux/ath9k_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "pci.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-wmac.h"
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#include "dev-usb.h"
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#include "dev-nfc.h"
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#include "machtypes.h"
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#define C60_GPIO_LED_PWR_AMBER 11
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#define C60_GPIO_LED_WLAN2_GREEN 12
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#define C60_GPIO_LED_WLAN2_AMBER 13
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#define C60_GPIO_LED_PWR_GREEN 16
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#define C60_GPIO_BTN_RESET 17
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/* GPIOs of the AR9300 PCIe chip */
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#define C60_GPIO_WMAC_LED_WLAN1_AMBER 0
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#define C60_GPIO_WMAC_LED_WLAN1_GREEN 3
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#define C60_KEYS_POLL_INTERVAL 20 /* msecs */
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#define C60_KEYS_DEBOUNCE_INTERVAL (3 * C60_KEYS_POLL_INTERVAL)
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#define C60_ART_ADDR 0x1f7f0000
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#define C60_ART_SIZE 0xffff
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#define C60_MAC_OFFSET 0
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#define C60_WMAC_CALDATA_OFFSET 0x1000
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#define C60_PCIE_CALDATA_OFFSET 0x5000
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static struct gpio_led c60_leds_gpio[] __initdata = {
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{
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.name = "c-60:amber:pwr",
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.gpio = C60_GPIO_LED_PWR_AMBER,
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.active_low = 1,
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},
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{
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.name = "c-60:green:pwr",
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.gpio = C60_GPIO_LED_PWR_GREEN,
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.active_low = 1,
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},
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{
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.name = "c-60:green:wlan2",
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.gpio = C60_GPIO_LED_WLAN2_GREEN,
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.active_low = 1,
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},
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{
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.name = "c-60:amber:wlan2",
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.gpio = C60_GPIO_LED_WLAN2_AMBER,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button c60_gpio_keys[] __initdata = {
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{
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.desc = "Reset button",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = C60_KEYS_DEBOUNCE_INTERVAL,
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.gpio = C60_GPIO_BTN_RESET,
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.active_low = 1,
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},
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};
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static struct ar8327_pad_cfg c60_ar8327_pad0_cfg = {
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.mode = AR8327_PAD_MAC_RGMII,
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.txclk_delay_en = true,
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.rxclk_delay_en = true,
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.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
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.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
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};
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static struct ar8327_platform_data c60_ar8327_data = {
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.pad0_cfg = &c60_ar8327_pad0_cfg,
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.port0_cfg = {
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.force_link = 1,
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.speed = AR8327_PORT_SPEED_1000,
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.duplex = 1,
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.txpause = 1,
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.rxpause = 1,
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}
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};
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static struct mdio_board_info c60_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 0,
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.platform_data = &c60_ar8327_data,
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},
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};
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static struct nand_ecclayout c60_nand_ecclayout = {
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.eccbytes = 7,
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.eccpos = { 4, 8, 9, 10, 13, 14, 15 },
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.oobavail = 9,
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.oobfree = { { 0, 3 }, { 6, 2 }, { 11, 2 }, }
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};
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static int c60_nand_scan_fixup(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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chip->ecc.size = 512;
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chip->ecc.strength = 4;
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chip->ecc.layout = &c60_nand_ecclayout;
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return 0;
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}
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static struct gpio_led c60_wmac0_leds_gpio[] = {
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{
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.name = "c-60:amber:wlan1",
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.gpio = C60_GPIO_WMAC_LED_WLAN1_AMBER,
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.active_low = 1,
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},
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{
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.name = "c-60:green:wlan1",
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.gpio = C60_GPIO_WMAC_LED_WLAN1_GREEN,
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.active_low = 1,
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},
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};
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static void __init c60_setup(void)
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{
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u8 tmpmac[6];
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u8 *art = (u8 *) KSEG1ADDR(C60_ART_ADDR);
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/* NAND */
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ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_SOFT_BCH);
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ath79_nfc_set_scan_fixup(c60_nand_scan_fixup);
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ath79_register_nfc();
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/* SPI Storage*/
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ath79_register_m25p80_large(NULL);
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/* AR8327 Switch Ethernet */
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
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mdiobus_register_board_info(c60_mdio0_info,
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ARRAY_SIZE(c60_mdio0_info));
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ath79_register_mdio(0, 0x0);
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/* GMAC0 is connected to an AR8327N switch */
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ath79_init_mac(ath79_eth0_data.mac_addr, art + C60_MAC_OFFSET, 0);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth0_pll_data.pll_1000 = 0x06000000;
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ath79_register_eth(0);
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/* LEDs & GPIO */
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ath79_register_leds_gpio(-1, ARRAY_SIZE(c60_leds_gpio),
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c60_leds_gpio);
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ath79_register_gpio_keys_polled(-1, C60_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(c60_gpio_keys),
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c60_gpio_keys);
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ap9x_pci_setup_wmac_leds(0, c60_wmac0_leds_gpio,
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ARRAY_SIZE(c60_wmac0_leds_gpio));
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/* USB */
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ath79_register_usb();
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/* WiFi */
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ath79_init_mac(tmpmac, art + C60_MAC_OFFSET, 1);
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ap91_pci_init(art + C60_PCIE_CALDATA_OFFSET, tmpmac);
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ath79_init_mac(tmpmac, art + C60_MAC_OFFSET, 2);
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ath79_register_wmac(art + C60_WMAC_CALDATA_OFFSET, tmpmac);
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}
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MIPS_MACHINE(ATH79_MACH_C60, "C-60", "AirTight Networks C-60",
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c60_setup);
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