kernel: bump 4.14 to 4.14.51
The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Refresh patches. Remove patch that can be reverse applied: mvebu/patches-4.14/530-ATA-ahci_mvebu-enable-stop_engine-override.patch mvebu/patches-4.14/531-ATA-ahci_mvebu-pmp-stop-errata-226.patch Update patch that no longer applied: ipq806x/patches-4.14/0035-clk-mux-Split-out-register-accessors-for-reuse.patch Compiled-tested-for: lantiq, ramips Run-tested-on: lantiq BT hh5a, ramips MIR3g Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> Tested-by: Michael Yartys <michael.yartys@protonmail.com> Tested-by: Rosen Penev <rosenp@gmail.com>v19.07.3_mercusys_ac12_duma
Kevin Darbyshire-Bryant
6 years ago
committed by
John Crispin
parent
31c26cece3
commit
094d49cddf
@ -1,12 +1,12 @@
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--- a/drivers/of/fdt.c
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+++ b/drivers/of/fdt.c
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@@ -1127,6 +1127,9 @@ int __init early_init_dt_scan_chosen(uns
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@@ -1130,6 +1130,9 @@ int __init early_init_dt_scan_chosen(uns
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p = of_get_flat_dt_prop(node, "bootargs", &l);
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if (p != NULL && l > 0)
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strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
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+ p = of_get_flat_dt_prop(node, "bootargs-append", &l);
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+ if (p != NULL && l > 0)
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+ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
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/*
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* CONFIG_CMDLINE is meant to be a default in case nothing else
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@ -1,224 +0,0 @@
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From fa89f53bd7288d6aa7a982841119e7123faf5a53 Mon Sep 17 00:00:00 2001
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From: Evan Wang <xswang@marvell.com>
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Date: Fri, 13 Apr 2018 12:32:30 +0800
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Subject: [PATCH] libahci: Allow drivers to override stop_engine
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Marvell armada37xx, armada7k and armada8k share the same
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AHCI sata controller IP, and currently there is an issue
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(Errata Ref#226)that the SATA can not be detected via SATA
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Port-MultiPlayer(PMP). After debugging, the reason is
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found that the value of Port-x FIS-based Switching Control
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(PxFBS@0x40) became wrong.
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According to design, the bits[11:8, 0] of register PxFBS
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are cleared when Port Command and Status (0x18) bit[0]
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changes its value from 1 to 0, i.e. falling edge of Port
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Command and Status bit[0] sends PULSE that resets PxFBS
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bits[11:8; 0].
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So it needs save the port PxFBS register before PxCMD
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ST write and restore the port PxFBS register afterwards
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in ahci_stop_engine().
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This commit allows drivers to override ahci_stop_engine
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behavior for use by the Marvell AHCI driver(and potentially
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other drivers in the future).
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Signed-off-by: Evan Wang <xswang@marvell.com>
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Cc: Ofer Heifetz <oferh@marvell.com>
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Cc: Tejun Heo <tj@kernel.org>
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Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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Signed-off-by: Tejun Heo <tj@kernel.org>
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---
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drivers/ata/ahci.c | 6 +++---
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drivers/ata/ahci.h | 7 +++++++
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drivers/ata/ahci_qoriq.c | 2 +-
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drivers/ata/ahci_xgene.c | 4 ++--
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drivers/ata/libahci.c | 20 ++++++++++++--------
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drivers/ata/sata_highbank.c | 2 +-
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6 files changed, 26 insertions(+), 15 deletions(-)
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diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
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index 1ff17799769d0..6389c88b3500a 100644
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--- a/drivers/ata/ahci.c
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+++ b/drivers/ata/ahci.c
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@@ -698,7 +698,7 @@ static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
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DPRINTK("ENTER\n");
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- ahci_stop_engine(ap);
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+ hpriv->stop_engine(ap);
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rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
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deadline, &online, NULL);
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@@ -724,7 +724,7 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
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bool online;
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int rc;
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- ahci_stop_engine(ap);
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+ hpriv->stop_engine(ap);
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/* clear D2H reception area to properly wait for D2H FIS */
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ata_tf_init(link->device, &tf);
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@@ -788,7 +788,7 @@ static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
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DPRINTK("ENTER\n");
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- ahci_stop_engine(ap);
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+ hpriv->stop_engine(ap);
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for (i = 0; i < 2; i++) {
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u16 val;
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diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
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index a9d996e17d75e..824bd399f02ea 100644
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--- a/drivers/ata/ahci.h
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+++ b/drivers/ata/ahci.h
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@@ -365,6 +365,13 @@ struct ahci_host_priv {
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* be overridden anytime before the host is activated.
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*/
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void (*start_engine)(struct ata_port *ap);
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+ /*
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+ * Optional ahci_stop_engine override, if not set this gets set to the
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+ * default ahci_stop_engine during ahci_save_initial_config, this can
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+ * be overridden anytime before the host is activated.
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+ */
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+ int (*stop_engine)(struct ata_port *ap);
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+
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irqreturn_t (*irq_handler)(int irq, void *dev_instance);
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/* only required for per-port MSI(-X) support */
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diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
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index 2685f28160f70..cfdef4d44ae92 100644
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--- a/drivers/ata/ahci_qoriq.c
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+++ b/drivers/ata/ahci_qoriq.c
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@@ -96,7 +96,7 @@ static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
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DPRINTK("ENTER\n");
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- ahci_stop_engine(ap);
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+ hpriv->stop_engine(ap);
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/*
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* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
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diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c
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index c2b5941d9184d..ad58da7c9affd 100644
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--- a/drivers/ata/ahci_xgene.c
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+++ b/drivers/ata/ahci_xgene.c
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@@ -165,7 +165,7 @@ static int xgene_ahci_restart_engine(struct ata_port *ap)
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PORT_CMD_ISSUE, 0x0, 1, 100))
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return -EBUSY;
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- ahci_stop_engine(ap);
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+ hpriv->stop_engine(ap);
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ahci_start_fis_rx(ap);
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/*
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@@ -421,7 +421,7 @@ static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
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portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
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portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
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- ahci_stop_engine(ap);
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+ hpriv->stop_engine(ap);
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rc = xgene_ahci_do_hardreset(link, deadline, &online);
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diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
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index 7adcf3caabd00..e5d90977caec2 100644
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--- a/drivers/ata/libahci.c
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+++ b/drivers/ata/libahci.c
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@@ -560,6 +560,9 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
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if (!hpriv->start_engine)
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hpriv->start_engine = ahci_start_engine;
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+ if (!hpriv->stop_engine)
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+ hpriv->stop_engine = ahci_stop_engine;
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+
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if (!hpriv->irq_handler)
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hpriv->irq_handler = ahci_single_level_irq_intr;
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}
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@@ -897,9 +900,10 @@ static void ahci_start_port(struct ata_port *ap)
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static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
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{
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int rc;
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+ struct ahci_host_priv *hpriv = ap->host->private_data;
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/* disable DMA */
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- rc = ahci_stop_engine(ap);
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+ rc = hpriv->stop_engine(ap);
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if (rc) {
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*emsg = "failed to stop engine";
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return rc;
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@@ -1310,7 +1314,7 @@ int ahci_kick_engine(struct ata_port *ap)
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int busy, rc;
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/* stop engine */
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- rc = ahci_stop_engine(ap);
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+ rc = hpriv->stop_engine(ap);
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if (rc)
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goto out_restart;
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@@ -1549,7 +1553,7 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
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DPRINTK("ENTER\n");
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- ahci_stop_engine(ap);
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+ hpriv->stop_engine(ap);
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/* clear D2H reception area to properly wait for D2H FIS */
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ata_tf_init(link->device, &tf);
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@@ -2075,14 +2079,14 @@ void ahci_error_handler(struct ata_port *ap)
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if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
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/* restart engine */
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- ahci_stop_engine(ap);
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+ hpriv->stop_engine(ap);
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hpriv->start_engine(ap);
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}
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sata_pmp_error_handler(ap);
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if (!ata_dev_enabled(ap->link.device))
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- ahci_stop_engine(ap);
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+ hpriv->stop_engine(ap);
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}
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EXPORT_SYMBOL_GPL(ahci_error_handler);
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@@ -2129,7 +2133,7 @@ static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
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return;
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/* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
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- rc = ahci_stop_engine(ap);
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+ rc = hpriv->stop_engine(ap);
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if (rc)
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return;
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@@ -2189,7 +2193,7 @@ static void ahci_enable_fbs(struct ata_port *ap)
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return;
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}
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- rc = ahci_stop_engine(ap);
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+ rc = hpriv->stop_engine(ap);
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if (rc)
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return;
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@@ -2222,7 +2226,7 @@ static void ahci_disable_fbs(struct ata_port *ap)
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return;
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}
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- rc = ahci_stop_engine(ap);
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+ rc = hpriv->stop_engine(ap);
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if (rc)
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return;
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diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
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index aafb8cc035232..e67815b896fcc 100644
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--- a/drivers/ata/sata_highbank.c
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+++ b/drivers/ata/sata_highbank.c
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@@ -410,7 +410,7 @@ static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
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int rc;
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int retry = 100;
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- ahci_stop_engine(ap);
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+ hpriv->stop_engine(ap);
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/* clear D2H reception area to properly wait for D2H FIS */
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ata_tf_init(link->device, &tf);
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@ -1,110 +0,0 @@
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From daa2e3bdbb0b3e691cf20a042350817310cb8cb5 Mon Sep 17 00:00:00 2001
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From: Evan Wang <xswang@marvell.com>
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Date: Fri, 13 Apr 2018 12:32:31 +0800
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Subject: [PATCH] ata: ahci: mvebu: override ahci_stop_engine for mvebu AHCI
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There is an issue(Errata Ref#226) that the SATA can not be
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detected via SATA Port-MultiPlayer(PMP) with following
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error log:
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ata1.15: PMP product ID mismatch
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ata1.15: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
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ata1.15: Port Multiplier vendor mismatch '0x1b4b'!='0x0'
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ata1.15: PMP revalidation failed (errno=-19)
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After debugging, the reason is found that the value Port-x
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FIS-based Switching Control(PxFBS@0x40) become wrong.
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According to design, the bits[11:8, 0] of register PxFBS
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are cleared when Port Command and Status (0x18) bit[0]
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changes its value from 1 to 0, i.e. falling edge of Port
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Command and Status bit[0] sends PULSE that resets PxFBS
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bits[11:8; 0].
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So it needs a mvebu SATA WA to save the port PxFBS register
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before PxCMD ST write and restore it afterwards.
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This patch implements the WA in a separate function of
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ahci_mvebu_stop_engine to override ahci_stop_gngine.
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Signed-off-by: Evan Wang <xswang@marvell.com>
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Cc: Ofer Heifetz <oferh@marvell.com>
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Cc: Tejun Heo <tj@kernel.org>
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Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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Signed-off-by: Tejun Heo <tj@kernel.org>
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---
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drivers/ata/ahci_mvebu.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 56 insertions(+)
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diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
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index de7128d81e9cc..0045dacd814b4 100644
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--- a/drivers/ata/ahci_mvebu.c
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+++ b/drivers/ata/ahci_mvebu.c
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@@ -62,6 +62,60 @@ static void ahci_mvebu_regret_option(struct ahci_host_priv *hpriv)
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writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
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}
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+/**
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+ * ahci_mvebu_stop_engine
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+ *
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+ * @ap: Target ata port
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+ *
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+ * Errata Ref#226 - SATA Disk HOT swap issue when connected through
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+ * Port Multiplier in FIS-based Switching mode.
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+ *
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+ * To avoid the issue, according to design, the bits[11:8, 0] of
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+ * register PxFBS are cleared when Port Command and Status (0x18) bit[0]
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+ * changes its value from 1 to 0, i.e. falling edge of Port
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+ * Command and Status bit[0] sends PULSE that resets PxFBS
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+ * bits[11:8; 0].
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+ *
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+ * This function is used to override function of "ahci_stop_engine"
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+ * from libahci.c by adding the mvebu work around(WA) to save PxFBS
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+ * value before the PxCMD ST write of 0, then restore PxFBS value.
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+ *
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+ * Return: 0 on success; Error code otherwise.
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+ */
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+int ahci_mvebu_stop_engine(struct ata_port *ap)
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+{
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+ void __iomem *port_mmio = ahci_port_base(ap);
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+ u32 tmp, port_fbs;
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+
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+ tmp = readl(port_mmio + PORT_CMD);
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+
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+ /* check if the HBA is idle */
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+ if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
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+ return 0;
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+
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+ /* save the port PxFBS register for later restore */
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+ port_fbs = readl(port_mmio + PORT_FBS);
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+
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+ /* setting HBA to idle */
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+ tmp &= ~PORT_CMD_START;
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+ writel(tmp, port_mmio + PORT_CMD);
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+
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+ /*
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+ * bit #15 PxCMD signal doesn't clear PxFBS,
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+ * restore the PxFBS register right after clearing the PxCMD ST,
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+ * no need to wait for the PxCMD bit #15.
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+ */
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+ writel(port_fbs, port_mmio + PORT_FBS);
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+
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+ /* wait for engine to stop. This could be as long as 500 msec */
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+ tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
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+ PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
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+ if (tmp & PORT_CMD_LIST_ON)
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+ return -EIO;
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+
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+ return 0;
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+}
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+
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#ifdef CONFIG_PM_SLEEP
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static int ahci_mvebu_suspend(struct platform_device *pdev, pm_message_t state)
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{
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@@ -112,6 +166,8 @@ static int ahci_mvebu_probe(struct platform_device *pdev)
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if (rc)
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return rc;
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+ hpriv->stop_engine = ahci_mvebu_stop_engine;
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+
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if (of_device_is_compatible(pdev->dev.of_node,
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"marvell,armada-380-ahci")) {
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dram = mv_mbus_dram_info();
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