kernel: update kernel 4.4 to version 4.4.69
Refresh patches. A number of patches have landed upstream & hence are no longer required locally: 062-[1-6]-MIPS-* series 042-0004-mtd-bcm47xxpart-fix-parsing-first-block Reintroduced lantiq/patches-4.4/0050-MIPS-Lantiq-Fix-cascaded-IRQ-setup as it was incorrectly included upstream thus dropped from LEDE. As it has now been reverted upstream it needs to be included again for LEDE. Run tested ar71xx Archer C7 v2 and lantiq. Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk> [update from 4.4.68 to 4.4.69] Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>v19.07.3_mercusys_ac12_duma
Kevin Darbyshire-Bryant
7 years ago
committed by
Hauke Mehrtens
parent
0a05fbd135
commit
088e28772c
@ -1,40 +0,0 @@
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From bd5d21310133921021d78995ad6346f908483124 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Sun, 20 Nov 2016 16:09:30 +0100
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Subject: [PATCH] mtd: bcm47xxpart: fix parsing first block after aligned TRX
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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After parsing TRX we should skip to the first block placed behind it.
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Our code was working only with TRX with length not aligned to the
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blocksize. In other cases (length aligned) it was missing the block
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places right after TRX.
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This fixes calculation and simplifies the comment.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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drivers/mtd/bcm47xxpart.c | 10 ++++------
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1 file changed, 4 insertions(+), 6 deletions(-)
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--- a/drivers/mtd/bcm47xxpart.c
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+++ b/drivers/mtd/bcm47xxpart.c
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@@ -229,12 +229,10 @@ static int bcm47xxpart_parse(struct mtd_
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last_trx_part = curr_part - 1;
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- /*
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- * We have whole TRX scanned, skip to the next part. Use
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- * roundown (not roundup), as the loop will increase
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- * offset in next step.
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- */
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- offset = rounddown(offset + trx->length, blocksize);
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+ /* Jump to the end of TRX */
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+ offset = roundup(offset + trx->length, blocksize);
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+ /* Next loop iteration will increase the offset */
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+ offset -= blocksize;
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continue;
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}
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@ -1,70 +0,0 @@
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From: Matt Redfearn <matt.redfearn@imgtec.com>
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Date: Mon, 19 Dec 2016 14:20:56 +0000
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Subject: [PATCH] MIPS: Introduce irq_stack
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Allocate a per-cpu irq stack for use within interrupt handlers.
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Also add a utility function on_irq_stack to determine if a given stack
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pointer is within the irq stack for that cpu.
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Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
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---
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--- a/arch/mips/include/asm/irq.h
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+++ b/arch/mips/include/asm/irq.h
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@@ -17,6 +17,18 @@
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#include <irq.h>
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+#define IRQ_STACK_SIZE THREAD_SIZE
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+
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+extern void *irq_stack[NR_CPUS];
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+
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+static inline bool on_irq_stack(int cpu, unsigned long sp)
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+{
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+ unsigned long low = (unsigned long)irq_stack[cpu];
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+ unsigned long high = low + IRQ_STACK_SIZE;
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+
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+ return (low <= sp && sp <= high);
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+}
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+
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#ifdef CONFIG_I8259
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static inline int irq_canonicalize(int irq)
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{
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--- a/arch/mips/kernel/asm-offsets.c
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+++ b/arch/mips/kernel/asm-offsets.c
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@@ -101,6 +101,7 @@ void output_thread_info_defines(void)
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OFFSET(TI_REGS, thread_info, regs);
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DEFINE(_THREAD_SIZE, THREAD_SIZE);
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DEFINE(_THREAD_MASK, THREAD_MASK);
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+ DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
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BLANK();
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}
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--- a/arch/mips/kernel/irq.c
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+++ b/arch/mips/kernel/irq.c
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@@ -25,6 +25,8 @@
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#include <linux/atomic.h>
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#include <asm/uaccess.h>
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+void *irq_stack[NR_CPUS];
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+
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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@@ -55,6 +57,15 @@ void __init init_IRQ(void)
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irq_set_noprobe(i);
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arch_init_irq();
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+
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+ for_each_possible_cpu(i) {
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+ int irq_pages = IRQ_STACK_SIZE / PAGE_SIZE;
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+ void *s = (void *)__get_free_pages(GFP_KERNEL, irq_pages);
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+
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+ irq_stack[i] = s;
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+ pr_debug("CPU%d IRQ stack at 0x%p - 0x%p\n", i,
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+ irq_stack[i], irq_stack[i] + IRQ_STACK_SIZE);
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+ }
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}
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#ifdef CONFIG_DEBUG_STACKOVERFLOW
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@ -1,42 +0,0 @@
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From: Matt Redfearn <matt.redfearn@imgtec.com>
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Date: Mon, 19 Dec 2016 14:20:57 +0000
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Subject: [PATCH] MIPS: Stack unwinding while on IRQ stack
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Within unwind stack, check if the stack pointer being unwound is within
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the CPU's irq_stack and if so use that page rather than the task's stack
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page.
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Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
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---
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--- a/arch/mips/kernel/process.c
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+++ b/arch/mips/kernel/process.c
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@@ -32,6 +32,7 @@
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#include <asm/cpu.h>
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#include <asm/dsp.h>
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#include <asm/fpu.h>
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+#include <asm/irq.h>
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#include <asm/msa.h>
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#include <asm/pgtable.h>
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#include <asm/mipsregs.h>
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@@ -552,7 +553,19 @@ EXPORT_SYMBOL(unwind_stack_by_address);
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unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
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unsigned long pc, unsigned long *ra)
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{
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- unsigned long stack_page = (unsigned long)task_stack_page(task);
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+ unsigned long stack_page = 0;
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+ int cpu;
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+
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+ for_each_possible_cpu(cpu) {
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+ if (on_irq_stack(cpu, *sp)) {
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+ stack_page = (unsigned long)irq_stack[cpu];
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+ break;
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+ }
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+ }
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+
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+ if (!stack_page)
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+ stack_page = (unsigned long)task_stack_page(task);
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+
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return unwind_stack_by_address(stack_page, sp, pc, ra);
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}
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#endif
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@ -1,48 +0,0 @@
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From: Matt Redfearn <matt.redfearn@imgtec.com>
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Date: Mon, 19 Dec 2016 14:20:58 +0000
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Subject: [PATCH] MIPS: Only change $28 to thread_info if coming from user
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mode
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The SAVE_SOME macro is used to save the execution context on all
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exceptions.
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If an exception occurs while executing user code, the stack is switched
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to the kernel's stack for the current task, and register $28 is switched
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to point to the current_thread_info, which is at the bottom of the stack
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region.
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If the exception occurs while executing kernel code, the stack is left,
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and this change ensures that register $28 is not updated. This is the
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correct behaviour when the kernel can be executing on the separate irq
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stack, because the thread_info will not be at the base of it.
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With this change, register $28 is only switched to it's kernel
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conventional usage of the currrent thread info pointer at the point at
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which execution enters kernel space. Doing it on every exception was
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redundant, but OK without an IRQ stack, but will be erroneous once that
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is introduced.
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Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
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Reviewed-by: Maciej W. Rozycki <macro@imgtec.com>
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---
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--- a/arch/mips/include/asm/stackframe.h
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+++ b/arch/mips/include/asm/stackframe.h
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@@ -216,12 +216,19 @@
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LONG_S $25, PT_R25(sp)
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LONG_S $28, PT_R28(sp)
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LONG_S $31, PT_R31(sp)
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+
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+ /* Set thread_info if we're coming from user mode */
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+ mfc0 k0, CP0_STATUS
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+ sll k0, 3 /* extract cu0 bit */
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+ bltz k0, 9f
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+
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ori $28, sp, _THREAD_MASK
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xori $28, _THREAD_MASK
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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.set mips64
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pref 0, 0($28) /* Prefetch the current pointer */
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#endif
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+9:
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.set pop
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.endm
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@ -1,116 +0,0 @@
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From: Matt Redfearn <matt.redfearn@imgtec.com>
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Date: Mon, 19 Dec 2016 14:20:59 +0000
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Subject: [PATCH] MIPS: Switch to the irq_stack in interrupts
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When enterring interrupt context via handle_int or except_vec_vi, switch
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to the irq_stack of the current CPU if it is not already in use.
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The current stack pointer is masked with the thread size and compared to
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the base or the irq stack. If it does not match then the stack pointer
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is set to the top of that stack, otherwise this is a nested irq being
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handled on the irq stack so the stack pointer should be left as it was.
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The in-use stack pointer is placed in the callee saved register s1. It
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will be saved to the stack when plat_irq_dispatch is invoked and can be
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restored once control returns here.
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Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
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---
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--- a/arch/mips/kernel/genex.S
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+++ b/arch/mips/kernel/genex.S
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@@ -188,9 +188,44 @@ NESTED(handle_int, PT_SIZE, sp)
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LONG_L s0, TI_REGS($28)
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LONG_S sp, TI_REGS($28)
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- PTR_LA ra, ret_from_irq
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- PTR_LA v0, plat_irq_dispatch
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- jr v0
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+
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+ /*
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+ * SAVE_ALL ensures we are using a valid kernel stack for the thread.
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+ * Check if we are already using the IRQ stack.
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+ */
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+ move s1, sp # Preserve the sp
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+
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+ /* Get IRQ stack for this CPU */
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+ ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
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+#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
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+ lui k1, %hi(irq_stack)
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+#else
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+ lui k1, %highest(irq_stack)
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+ daddiu k1, %higher(irq_stack)
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+ dsll k1, 16
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+ daddiu k1, %hi(irq_stack)
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+ dsll k1, 16
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+#endif
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+ LONG_SRL k0, SMP_CPUID_PTRSHIFT
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+ LONG_ADDU k1, k0
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+ LONG_L t0, %lo(irq_stack)(k1)
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+
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+ # Check if already on IRQ stack
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+ PTR_LI t1, ~(_THREAD_SIZE-1)
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+ and t1, t1, sp
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+ beq t0, t1, 2f
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+
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+ /* Switch to IRQ stack */
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+ li t1, _IRQ_STACK_SIZE
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+ PTR_ADD sp, t0, t1
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+
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+2:
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+ jal plat_irq_dispatch
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+
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+ /* Restore sp */
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+ move sp, s1
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+
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+ j ret_from_irq
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#ifdef CONFIG_CPU_MICROMIPS
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nop
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#endif
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@@ -263,8 +298,44 @@ NESTED(except_vec_vi_handler, 0, sp)
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LONG_L s0, TI_REGS($28)
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LONG_S sp, TI_REGS($28)
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- PTR_LA ra, ret_from_irq
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- jr v0
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+
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+ /*
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+ * SAVE_ALL ensures we are using a valid kernel stack for the thread.
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+ * Check if we are already using the IRQ stack.
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+ */
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+ move s1, sp # Preserve the sp
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+
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+ /* Get IRQ stack for this CPU */
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+ ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
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+#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
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+ lui k1, %hi(irq_stack)
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+#else
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+ lui k1, %highest(irq_stack)
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+ daddiu k1, %higher(irq_stack)
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+ dsll k1, 16
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+ daddiu k1, %hi(irq_stack)
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+ dsll k1, 16
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+#endif
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+ LONG_SRL k0, SMP_CPUID_PTRSHIFT
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+ LONG_ADDU k1, k0
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+ LONG_L t0, %lo(irq_stack)(k1)
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+
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+ # Check if already on IRQ stack
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+ PTR_LI t1, ~(_THREAD_SIZE-1)
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+ and t1, t1, sp
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+ beq t0, t1, 2f
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+
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+ /* Switch to IRQ stack */
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+ li t1, _IRQ_STACK_SIZE
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+ PTR_ADD sp, t0, t1
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+
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+2:
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+ jal plat_irq_dispatch
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+
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+ /* Restore sp */
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+ move sp, s1
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+
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+ j ret_from_irq
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END(except_vec_vi_handler)
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/*
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@ -1,21 +0,0 @@
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From: Matt Redfearn <matt.redfearn@imgtec.com>
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Date: Mon, 19 Dec 2016 14:21:00 +0000
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Subject: [PATCH] MIPS: Select HAVE_IRQ_EXIT_ON_IRQ_STACK
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Since do_IRQ is now invoked on a separate IRQ stack, we select
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HAVE_IRQ_EXIT_ON_IRQ_STACK so that softirq's may be invoked directly
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from irq_exit(), rather than requiring do_softirq_own_stack.
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Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
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---
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -9,6 +9,7 @@ config MIPS
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select HAVE_CONTEXT_TRACKING
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select HAVE_GENERIC_DMA_COHERENT
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select HAVE_IDE
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+ select HAVE_IRQ_EXIT_ON_IRQ_STACK
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select HAVE_OPROFILE
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select HAVE_PERF_EVENTS
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select PERF_USE_VMALLOC
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@ -1,35 +0,0 @@
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From de856416e7143e32afc4849625616554aa060f7a Mon Sep 17 00:00:00 2001
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From: Matt Redfearn <matt.redfearn@imgtec.com>
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Date: Wed, 25 Jan 2017 17:00:25 +0000
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Subject: [PATCH] MIPS: IRQ Stack: Fix erroneous jal to plat_irq_dispatch
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Commit dda45f701c9d ("MIPS: Switch to the irq_stack in interrupts")
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changed both the normal and vectored interrupt handlers. Unfortunately
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the vectored version, "except_vec_vi_handler", was incorrectly modified
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to unconditionally jal to plat_irq_dispatch, rather than doing a jalr to
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the vectored handler that has been set up. This is ok for many platforms
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which set the vectored handler to plat_irq_dispatch anyway, but will
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cause problems with platforms that use other handlers.
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Fixes: dda45f701c9d ("MIPS: Switch to the irq_stack in interrupts")
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Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
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Cc: Ralf Baechle <ralf@linux-mips.org>
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Cc: Paul Burton <paul.burton@imgtec.com>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/15110/
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Signed-off-by: James Hogan <james.hogan@imgtec.com>
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---
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arch/mips/kernel/genex.S | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/mips/kernel/genex.S
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+++ b/arch/mips/kernel/genex.S
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@@ -330,7 +330,7 @@ NESTED(except_vec_vi_handler, 0, sp)
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PTR_ADD sp, t0, t1
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2:
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- jal plat_irq_dispatch
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+ jalr v0
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/* Restore sp */
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move sp, s1
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@ -0,0 +1,87 @@
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From: Felix Fietkau <nbd@nbd.name>
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Date: Thu, 19 Jan 2017 12:14:44 +0100
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Subject: [PATCH] MIPS: Lantiq: Fix cascaded IRQ setup
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With the IRQ stack changes integrated, the XRX200 devices started
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emitting a constant stream of kernel messages like this:
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[ 565.415310] Spurious IRQ: CAUSE=0x1100c300
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This appears to be caused by IP0 firing for some reason without being
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handled. Fix this by setting up IP2-6 as a proper chained IRQ handler and
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calling do_IRQ for all MIPS CPU interrupts.
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Cc: john@phrozen.org
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Cc: stable@vger.kernel.org
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/mips/lantiq/irq.c
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+++ b/arch/mips/lantiq/irq.c
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@@ -271,6 +271,11 @@ static void ltq_hw5_irqdispatch(void)
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DEFINE_HWx_IRQDISPATCH(5)
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#endif
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+static void ltq_hw_irq_handler(struct irq_desc *desc)
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+{
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+ ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
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+}
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+
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#ifdef CONFIG_MIPS_MT_SMP
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void __init arch_init_ipiirq(int irq, struct irqaction *action)
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{
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@@ -315,23 +320,19 @@ static struct irqaction irq_call = {
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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- unsigned int i;
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+ int irq;
|
||||
|
||||
- if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
|
||||
- do_IRQ(MIPS_CPU_TIMER_IRQ);
|
||||
- goto out;
|
||||
- } else {
|
||||
- for (i = 0; i < MAX_IM; i++) {
|
||||
- if (pending & (CAUSEF_IP2 << i)) {
|
||||
- ltq_hw_irqdispatch(i);
|
||||
- goto out;
|
||||
- }
|
||||
- }
|
||||
+ if (!pending) {
|
||||
+ spurious_interrupt();
|
||||
+ return;
|
||||
}
|
||||
- pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
|
||||
|
||||
-out:
|
||||
- return;
|
||||
+ pending >>= CAUSEB_IP;
|
||||
+ while (pending) {
|
||||
+ irq = fls(pending) - 1;
|
||||
+ do_IRQ(MIPS_CPU_IRQ_BASE + irq);
|
||||
+ pending &= ~BIT(irq);
|
||||
+ }
|
||||
}
|
||||
|
||||
static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
||||
@@ -356,11 +357,6 @@ static const struct irq_domain_ops irq_d
|
||||
.map = icu_map,
|
||||
};
|
||||
|
||||
-static struct irqaction cascade = {
|
||||
- .handler = no_action,
|
||||
- .name = "cascade",
|
||||
-};
|
||||
-
|
||||
int __init icu_of_init(struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
struct device_node *eiu_node;
|
||||
@@ -392,7 +388,7 @@ int __init icu_of_init(struct device_nod
|
||||
mips_cpu_irq_init();
|
||||
|
||||
for (i = 0; i < MAX_IM; i++)
|
||||
- setup_irq(i + 2, &cascade);
|
||||
+ irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
|
||||
|
||||
if (cpu_has_vint) {
|
||||
pr_info("Setting up vectored interrupts\n");
|
||||
Loading…
Reference in New Issue