add preliminary AR9 support attention: if caches enabled the network is broken attention: the network of the flash image doesn't work because of enabled caches
SVN-Revision: 20606v19.07.3_mercusys_ac12_duma
Ralph Hempel
14 years ago
parent
aa323e0134
commit
046d73d3c2
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@ -0,0 +1,47 @@
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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#COBJS := $(BOARD).o
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COBJS-y += ar9.o
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SOBJS = lowlevel_init.o pmuenable.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,666 @@
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2010
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* Thomas Langer, Ralph Hempel
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/addrspace.h>
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#include <asm/ar9.h>
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#include <asm/reboot.h>
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#include <asm/io.h>
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#if defined(CONFIG_CMD_HTTPD)
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#include <httpd.h>
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#endif
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extern ulong ifx_get_ddr_hz(void);
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extern ulong ifx_get_cpuclk(void);
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/* definitions for external PHYs / Switches */
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/* Split values into phy address and register address */
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#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
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/* IDs and registers of known external switches */
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#define ID_SAMURAI_0 0x1020
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#define ID_SAMURAI_1 0x0007
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#define SAMURAI_ID_REG0 0xA0
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#define SAMURAI_ID_REG1 0xA1
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#define ID_TANTOS 0x2599
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#define RGMII_MODE 0
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#define MII_MODE 1
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#define REV_MII_MODE 2
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#define RED_MII_MODE_IC 3 /*Input clock */
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#define RGMII_MODE_100MB 4
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#define TURBO_REV_MII_MODE 6 /*Turbo Rev Mii mode */
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#define RED_MII_MODE_OC 7 /*Output clock */
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#define RGMII_MODE_10MB 8
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#define mdelay(n) udelay((n)*1000)
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static void ar9_sw_chip_init(u8 port, u8 mode);
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static void ar9_enable_sw_port(u8 port, u8 state);
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static void ar9_configure_sw_port(u8 port, u8 mode);
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static u16 ar9_smi_reg_read(u16 reg);
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static u16 ar9_smi_reg_write(u16 reg, u16 data);
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static char * const name = "lq_cpe_eth";
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static int external_switch_init(void);
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void _machine_restart(void)
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{
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*AR9_RCU_RST_REQ |= AR9_RST_ALL;
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}
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#ifdef CONFIG_SYS_RAMBOOT
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phys_size_t initdram(int board_type)
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{
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return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
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}
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#elif defined(CONFIG_USE_DDR_RAM)
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phys_size_t initdram(int board_type)
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{
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return (CONFIG_SYS_MAX_RAM);
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}
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#else
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static ulong max_sdram_size(void) /* per Chip Select */
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{
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/* The only supported SDRAM data width is 16bit.
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*/
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#define CFG_DW 4
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/* The only supported number of SDRAM banks is 4.
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*/
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#define CFG_NB 4
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ulong cfgpb0 = *AR9_SDRAM_MC_CFGPB0;
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int cols = cfgpb0 & 0xF;
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int rows = (cfgpb0 & 0xF0) >> 4;
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ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
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return size;
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}
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'.
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*/
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static long int dram_size(long int *base, long int maxsize)
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{
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof (long));
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}
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}
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return (maxsize);
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}
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phys_size_t initdram(int board_type)
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{
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int rows, cols, best_val = *AR9_SDRAM_MC_CFGPB0;
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ulong size, max_size = 0;
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ulong our_address;
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/* load t9 into our_address */
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asm volatile ("move %0, $25" : "=r" (our_address) :);
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/* Can't probe for RAM size unless we are running from Flash.
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* find out whether running from DRAM or Flash.
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*/
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if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
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{
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return max_sdram_size();
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}
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for (cols = 0x8; cols <= 0xC; cols++)
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{
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for (rows = 0xB; rows <= 0xD; rows++)
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{
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*AR9_SDRAM_MC_CFGPB0 = (0x14 << 8) |
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(rows << 4) | cols;
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size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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max_sdram_size());
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if (size > max_size)
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{
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best_val = *AR9_SDRAM_MC_CFGPB0;
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max_size = size;
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}
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}
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}
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*AR9_SDRAM_MC_CFGPB0 = best_val;
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return max_size;
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}
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#endif
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int checkboard (void)
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{
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unsigned long chipid = *AR9_MPS_CHIPID;
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int part_num;
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puts ("Board: ");
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part_num = AR9_MPS_CHIPID_PARTNUM_GET(chipid);
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switch (part_num)
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{
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case 0x16C:
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puts("ARX188 ");
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break;
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case 0x16D:
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puts("ARX168 ");
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break;
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case 0x16F:
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puts("ARX182 ");
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break;
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case 0x170:
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puts("GRX188 ");
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break;
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case 0x171:
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puts("GRX168 ");
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break;
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default:
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printf ("unknown, chip part number 0x%03X ", part_num);
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break;
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}
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printf ("V1.%ld, ", AR9_MPS_CHIPID_VERSION_GET(chipid));
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printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
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printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
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return 0;
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}
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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int board_early_init_f(void)
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{
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#ifdef CONFIG_EBU_ADDSEL0
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(*AR9_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
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#endif
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#ifdef CONFIG_EBU_ADDSEL1
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(*AR9_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
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#endif
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#ifdef CONFIG_EBU_ADDSEL2
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(*AR9_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
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#endif
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#ifdef CONFIG_EBU_ADDSEL3
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(*AR9_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
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#endif
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#ifdef CONFIG_EBU_BUSCON0
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(*AR9_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
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#endif
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#ifdef CONFIG_EBU_BUSCON1
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(*AR9_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
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#endif
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#ifdef CONFIG_EBU_BUSCON2
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(*AR9_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
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#endif
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#ifdef CONFIG_EBU_BUSCON3
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(*AR9_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
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#endif
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return 0;
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}
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_IFX_ETOP)
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*AR9_PMU_PWDCR &= 0xFFFFEFDF;
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*AR9_PMU_PWDCR &= ~AR9_PMU_DMA; /* enable DMA from PMU */
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if (lq_eth_initialize(bis) < 0)
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return -1;
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*AR9_RCU_RST_REQ |= 1;
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udelay(200000);
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*AR9_RCU_RST_REQ &= (unsigned long)~1;
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udelay(1000);
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#ifdef CONFIG_EXTRA_SWITCH
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if (external_switch_init()<0)
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return -1;
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#endif /* CONFIG_EXTRA_SWITCH */
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#endif /* CONFIG_IFX_ETOP */
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return 0;
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}
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static void ar9_configure_sw_port(u8 port, u8 mode)
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{
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if(port)
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{
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if (mode == 1) //MII mode
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{
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*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
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*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
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*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0xf000)) | 0x2000;
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*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x2000;
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}
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else if(mode == 2 || mode == 6) //Rev Mii mode
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{
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*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
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*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
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*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0xf000)) & ~0x2000;
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*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xd000;
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}
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}
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else //Port 0
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{
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if (mode == 1) //MII mode
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{
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*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
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*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
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*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0x0303)) | 0x0100;
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*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0100;
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}
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else if(mode ==2 || mode ==6) //Rev Mii mode
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{
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*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
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*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
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*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0x0303)) & ~0x0100;
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*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0203;
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}
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}
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}
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/*
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Call this function to place either MAC port 0 or 1 into working mode.
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Parameters:
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port - select ports 0 or 1.
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state of interface : state
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0: RGMII
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1: MII
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2: Rev MII
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3: Reduce MII (input clock)
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4: RGMII 100mb
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5: Reserve
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6: Turbo Rev MII
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7: Reduce MII (output clock)
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*/
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void ar9_enable_sw_port(u8 port, u8 state)
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{
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REG32(AR9_SW_GCTL0) |= 0x80000000;
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if (port == 0)
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{
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REG32(AR9_SW_RGMII_CTL) &= 0xffcffc0e ;
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//#if AR9_REFBOARD_TANTOS
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REG32(0xbf20302c) &= 0xffff81ff;
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REG32(0xbf20302c) |= 4<<9 ;
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//#endif
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REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<8;
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if((state &0x3) == 0)
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{
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REG32(AR9_SW_RGMII_CTL) &= 0xfffffff3;
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if(state == 4)
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REG32(AR9_SW_RGMII_CTL) |= 0x4;
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else
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REG32(AR9_SW_RGMII_CTL) |= 0x8;
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}
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if(state == 6)
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REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<20));
|
||||
if(state == 7)
|
||||
REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<21));
|
||||
}
|
||||
// *AR9_PPE32_ETOP_CFG = *AR9_PPE32_ETOP_CFG & 0xfffffffe;
|
||||
else
|
||||
{
|
||||
REG32(AR9_SW_RGMII_CTL) &= 0xff303fff ;
|
||||
REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<18;
|
||||
if((state &0x3) == 0)
|
||||
{
|
||||
REG32(AR9_SW_RGMII_CTL) &= 0xffffcfff;
|
||||
if(state == 4)
|
||||
REG32(AR9_SW_RGMII_CTL) |= 0x1000;
|
||||
else
|
||||
REG32(AR9_SW_RGMII_CTL) |= 0x2000;
|
||||
}
|
||||
if(state == 6)
|
||||
REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<22));
|
||||
if(state == 7)
|
||||
REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<23));
|
||||
}
|
||||
}
|
||||
|
||||
void pci_reset(void)
|
||||
{
|
||||
int i,j;
|
||||
#define AR9_V1_PCI_RST_FIX 1
|
||||
#if AR9_V1_PCI_RST_FIX // 5th June 2008 Add GPIO19 to control EJTAG_TRST
|
||||
*AR9_GPIO_P1_ALTSEL0 = *AR9_GPIO_P1_ALTSEL0 & ~0x8;
|
||||
*AR9_GPIO_P1_ALTSEL1 = *AR9_GPIO_P1_ALTSEL1 & ~0x8;
|
||||
*AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR | 0x8;
|
||||
*AR9_GPIO_P1_OD = *AR9_GPIO_P1_OD | 0x8;
|
||||
*AR9_GPIO_P1_OUT = *AR9_GPIO_P1_OUT | 0x8;
|
||||
*AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 & ~0x4000;
|
||||
*AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~0x4000;
|
||||
*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | 0x4000;
|
||||
*AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | 0x4000;
|
||||
for(j=0;j<5;j++) {
|
||||
*AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT & ~0x4000;
|
||||
for(i=0;i<0x10000;i++);
|
||||
*AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT | 0x4000;
|
||||
for(i=0;i<0x10000;i++);
|
||||
}
|
||||
*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR & ~0x4000;
|
||||
*AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR & ~0x8;
|
||||
#endif
|
||||
}
|
||||
|
||||
static u16 ar9_smi_reg_read(u16 reg)
|
||||
{
|
||||
int i;
|
||||
while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
|
||||
REG32(AR9_SW_MDIO_CTL) = 0x8000| 0x2<<10 | ((u32) (reg&0x3ff)) ; /*0x10=MDIO_OP_READ*/
|
||||
for(i=0;i<0x3fff;i++);
|
||||
udelay(50);
|
||||
while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
|
||||
return((u16) (REG32(AR9_SW_MDIO_DATA)));
|
||||
}
|
||||
|
||||
static u16 ar9_smi_reg_write(u16 reg, u16 data)
|
||||
{
|
||||
int i;
|
||||
while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
|
||||
REG32(AR9_SW_MDIO_CTL) = 0x8000| (((u32) data)<<16) | 0x01<<10 | ((u32) (reg&0x3ff)) ; /*0x01=MDIO_OP_WRITE*/
|
||||
for(i=0;i<0x3fff;i++);
|
||||
udelay(50);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ar9_sw_chip_init(u8 port, u8 mode)
|
||||
{
|
||||
int i;
|
||||
u16 chipid;
|
||||
|
||||
debug("\nsearching for switches ... ");
|
||||
|
||||
asm("sync");
|
||||
pci_reset();
|
||||
|
||||
/* 25mhz clock out */
|
||||
*AR9_CGU_IFCCR &= ~(3<<10);
|
||||
*AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 | (1<<3);
|
||||
*AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~(1<<3);
|
||||
*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | (1<<3);
|
||||
*AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | (1<<3);
|
||||
*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 & ~(1<<0);
|
||||
*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(1<<0);
|
||||
*AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | (1<<0);
|
||||
*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | (1<<0);
|
||||
|
||||
*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & 0xFFFBDFDF) ;
|
||||
*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & ~(AR9_PMU_DMA | AR9_PMU_SWITCH));
|
||||
*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR | AR9_PMU_USB0 | AR9_PMU_USB0_P);
|
||||
|
||||
*AR9_GPIO_P2_OUT &= ~(1<<0);
|
||||
asm("sync");
|
||||
|
||||
ar9_configure_sw_port(port, mode);
|
||||
ar9_enable_sw_port(port, mode);
|
||||
REG32(AR9_SW_P0_CTL) |= 0x400000; /* disable mdio polling for tantos */
|
||||
asm("sync");
|
||||
|
||||
/*GPIO 55(P3.7) used as output, set high*/
|
||||
*AR9_GPIO_P3_OD |=(1<<7);
|
||||
*AR9_GPIO_P3_DIR |= (1<<7);
|
||||
*AR9_GPIO_P3_ALTSEL0 &=~(1<<7);
|
||||
*AR9_GPIO_P3_ALTSEL1 &=~(1<<7);
|
||||
asm("sync");
|
||||
udelay(10);
|
||||
|
||||
*AR9_GPIO_P3_OUT &= ~(1<<7);
|
||||
for(i=0;i<1000;i++)
|
||||
udelay(110);
|
||||
*AR9_GPIO_P3_OUT |=(1<<7);
|
||||
udelay(100);
|
||||
|
||||
if(port==0)
|
||||
REG32(AR9_SW_P0_CTL) |= 0x40001;
|
||||
else
|
||||
REG32(AR9_SW_P1_CTL) |= 0x40001;
|
||||
|
||||
REG32(AR9_SW_P2_CTL) |= 0x40001;
|
||||
REG32(AR9_SW_PMAC_HD_CTL) |= 0x40000; /* enable CRC */
|
||||
|
||||
*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xc00);
|
||||
*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xc00);
|
||||
*AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | 0xc00;
|
||||
*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xc00;
|
||||
|
||||
asm("sync");
|
||||
chipid = (unsigned short)(ar9_smi_reg_read(0x101));
|
||||
printf("\nswitch chip id=%08x\n",chipid);
|
||||
if (chipid != ID_TANTOS) {
|
||||
debug("whatever detected\n");
|
||||
ar9_smi_reg_write(0x1,0x840f);
|
||||
ar9_smi_reg_write(0x3,0x840f);
|
||||
ar9_smi_reg_write(0x5,0x840f);
|
||||
ar9_smi_reg_write(0x7,0x840f);
|
||||
ar9_smi_reg_write(0x8,0x840f);
|
||||
ar9_smi_reg_write(0x12,0x3602);
|
||||
#ifdef CLK_OUT2_25MHZ
|
||||
ar9_smi_reg_write(0x33,0x4000);
|
||||
#endif
|
||||
} else { // Tantos switch ship
|
||||
debug("Tantos switch detected\n");
|
||||
ar9_smi_reg_write(0xa1,0x0004); /*port 5 force link up*/
|
||||
ar9_smi_reg_write(0xc1,0x0004); /*port 6 force link up*/
|
||||
ar9_smi_reg_write(0xf5,0x0BBB); /*port 4 duplex mode, flow control enable,1000Mbit/s*/
|
||||
/*port 5 duplex mode, flow control enable, 1000Mbit/s*/
|
||||
/*port 6 duplex mode, flow control enable, 1000Mbit/s*/
|
||||
}
|
||||
asm("sync");
|
||||
|
||||
/*reset GPHY*/
|
||||
mdelay(200);
|
||||
*AR9_RCU_RST_REQ |= (AR9_RCU_RST_REQ_DMA | AR9_RCU_RST_REQ_PPE) ;
|
||||
udelay(50);
|
||||
*AR9_GPIO_P2_OUT |= (1<<0);
|
||||
}
|
||||
|
||||
static void ar9_dma_init(void)
|
||||
{
|
||||
/* select port */
|
||||
*AR9_DMA_PS = 0;
|
||||
|
||||
/*
|
||||
TXWGT 14:12 rw Port Weight for Transmit Direction (the default value “001”)
|
||||
|
||||
TXENDI 11:10 rw Endianness for Transmit Direction
|
||||
Determine a byte swap between memory interface (left hand side) and
|
||||
peripheral interface (right hand side).
|
||||
00B B0_B1_B2_B3 No byte switching
|
||||
01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
|
||||
10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
|
||||
|
||||
RXENDI 9:8 rw Endianness for Receive Direction
|
||||
Determine a byte swap between peripheral (left hand side) and memory
|
||||
interface (right hand side).
|
||||
00B B0_B1_B2_B3 No byte switching
|
||||
01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
|
||||
10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
|
||||
11B B3_B2_B1_B0 B0B1B2B3 => B3B2B1B0
|
||||
|
||||
TXBL 5:4 rw Burst Length for Transmit Direction
|
||||
Selects burst length for TX direction.
|
||||
Others are reserved and will result in 2_WORDS burst length.
|
||||
01B 2_WORDS 2 words
|
||||
10B 4_WORDS 4 words
|
||||
11B 8_WORDS 8 words
|
||||
|
||||
RXBL 3:2 rw Burst Length for Receive Direction
|
||||
Selects burst length for RX direction.
|
||||
Others are reserved and will result in 2_WORDS burst length.
|
||||
01B 2_WORDS 2 words
|
||||
10B 4_WORDS 4 words
|
||||
11B 8_WORDS 8 words
|
||||
*/
|
||||
*AR9_DMA_PCTRL = 0x1f28;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_EXTRA_SWITCH
|
||||
static int external_switch_init(void)
|
||||
{
|
||||
ar9_sw_chip_init(0, RGMII_MODE);
|
||||
|
||||
ar9_dma_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_EXTRA_SWITCH */
|
||||
|
||||
#if defined(CONFIG_CMD_HTTPD)
|
||||
|
||||
static int image_info (ulong addr)
|
||||
{
|
||||
void *hdr = (void *)addr;
|
||||
|
||||
printf ("\n## Checking Image at %08lx ...\n", addr);
|
||||
|
||||
switch (genimg_get_format (hdr)) {
|
||||
case IMAGE_FORMAT_LEGACY:
|
||||
puts (" Legacy image found\n");
|
||||
if (!image_check_magic (hdr)) {
|
||||
puts (" Bad Magic Number\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (!image_check_hcrc (hdr)) {
|
||||
puts (" Bad Header Checksum\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
image_print_contents (hdr);
|
||||
|
||||
puts (" Verifying Checksum ... ");
|
||||
if (!image_check_dcrc (hdr)) {
|
||||
puts (" Bad Data CRC\n");
|
||||
return 1;
|
||||
}
|
||||
puts ("OK\n");
|
||||
return 0;
|
||||
#if defined(CONFIG_FIT)
|
||||
case IMAGE_FORMAT_FIT:
|
||||
puts (" FIT image found\n");
|
||||
|
||||
if (!fit_check_format (hdr)) {
|
||||
puts ("Bad FIT image format!\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
fit_print_contents (hdr);
|
||||
|
||||
if (!fit_all_image_check_hashes (hdr)) {
|
||||
puts ("Bad hash in FIT image!\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
default:
|
||||
puts ("Unknown image format!\n");
|
||||
break;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int do_http_upgrade(const unsigned char *data, const ulong size)
|
||||
{
|
||||
/* check the image */
|
||||
if(image_info(data)) {
|
||||
return -1;
|
||||
}
|
||||
/* write the image to the flash */
|
||||
puts("http ugrade ...\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_http_progress(const int state)
|
||||
{
|
||||
/* toggle LED's here */
|
||||
switch(state) {
|
||||
case HTTP_PROGRESS_START:
|
||||
puts("http start\n");
|
||||
break;
|
||||
case HTTP_PROGRESS_TIMEOUT:
|
||||
break;
|
||||
case HTTP_PROGRESS_UPLOAD_READY:
|
||||
puts("http upload ready\n");
|
||||
break;
|
||||
case HTTP_PROGRESS_UGRADE_READY:
|
||||
puts("http ugrade ready\n");
|
||||
break;
|
||||
case HTTP_PROGRESS_UGRADE_FAILED:
|
||||
puts("http ugrade failed\n");
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long do_http_tmp_address(void)
|
||||
{
|
||||
char *s = getenv ("ram_addr");
|
||||
if (s) {
|
||||
ulong tmp = simple_strtoul (s, NULL, 16);
|
||||
return tmp;
|
||||
}
|
||||
return 0 /*0x80a00000*/;
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,51 @@
|
||||
/* Settings for Denali DDR SDRAM controller */
|
||||
/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
|
||||
|
||||
#define MC_DC0_VALUE 0x1B1B
|
||||
#define MC_DC1_VALUE 0x0
|
||||
#define MC_DC2_VALUE 0x0
|
||||
#define MC_DC3_VALUE 0x0
|
||||
#define MC_DC4_VALUE 0x0
|
||||
#define MC_DC5_VALUE 0x200
|
||||
#define MC_DC6_VALUE 0x306
|
||||
#define MC_DC7_VALUE 0x303
|
||||
#define MC_DC8_VALUE 0x102
|
||||
#define MC_DC9_VALUE 0x70a
|
||||
#define MC_DC10_VALUE 0x203
|
||||
#define MC_DC11_VALUE 0xc02
|
||||
#define MC_DC12_VALUE 0x1C8
|
||||
#define MC_DC13_VALUE 0x1
|
||||
#define MC_DC14_VALUE 0x0
|
||||
#define MC_DC15_VALUE 0x139 /* WDQS tuning for clk_wr*/
|
||||
#define MC_DC16_VALUE 0x2200
|
||||
#define MC_DC17_VALUE 0xd
|
||||
#define MC_DC18_VALUE 0x301
|
||||
#define MC_DC19_VALUE 0x200
|
||||
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
|
||||
#define MC_DC21_VALUE 0x1800
|
||||
#define MC_DC22_VALUE 0x1818
|
||||
#define MC_DC23_VALUE 0x0
|
||||
#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */
|
||||
#define MC_DC25_VALUE 0x0
|
||||
#define MC_DC26_VALUE 0x0
|
||||
#define MC_DC27_VALUE 0x0
|
||||
#define MC_DC28_VALUE 0x514
|
||||
#define MC_DC29_VALUE 0x2d93
|
||||
#define MC_DC30_VALUE 0x8235
|
||||
#define MC_DC31_VALUE 0x0
|
||||
#define MC_DC32_VALUE 0x0
|
||||
#define MC_DC33_VALUE 0x0
|
||||
#define MC_DC34_VALUE 0x0
|
||||
#define MC_DC35_VALUE 0x0
|
||||
#define MC_DC36_VALUE 0x0
|
||||
#define MC_DC37_VALUE 0x0
|
||||
#define MC_DC38_VALUE 0x0
|
||||
#define MC_DC39_VALUE 0x0
|
||||
#define MC_DC40_VALUE 0x0
|
||||
#define MC_DC41_VALUE 0x0
|
||||
#define MC_DC42_VALUE 0x0
|
||||
#define MC_DC43_VALUE 0x0
|
||||
#define MC_DC44_VALUE 0x0
|
||||
#define MC_DC45_VALUE 0x600
|
||||
//#define MC_DC45_VALUE 0x400
|
||||
#define MC_DC46_VALUE 0x0
|
||||
@ -0,0 +1,51 @@
|
||||
/* Settings for Denali DDR SDRAM controller */
|
||||
/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
|
||||
|
||||
#define MC_DC0_VALUE 0x1B1B
|
||||
#define MC_DC1_VALUE 0x0
|
||||
#define MC_DC2_VALUE 0x0
|
||||
#define MC_DC3_VALUE 0x0
|
||||
#define MC_DC4_VALUE 0x0
|
||||
#define MC_DC5_VALUE 0x200
|
||||
#define MC_DC6_VALUE 0x306
|
||||
#define MC_DC7_VALUE 0x303
|
||||
#define MC_DC8_VALUE 0x102
|
||||
#define MC_DC9_VALUE 0x70a
|
||||
#define MC_DC10_VALUE 0x203
|
||||
#define MC_DC11_VALUE 0xc02
|
||||
#define MC_DC12_VALUE 0x1C8
|
||||
#define MC_DC13_VALUE 0x1
|
||||
#define MC_DC14_VALUE 0x0
|
||||
#define MC_DC15_VALUE 0x13f /* WDQS tuning for clk_wr*/
|
||||
#define MC_DC16_VALUE 0x2200
|
||||
#define MC_DC17_VALUE 0xd
|
||||
#define MC_DC18_VALUE 0x301
|
||||
#define MC_DC19_VALUE 0x200
|
||||
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
|
||||
#define MC_DC21_VALUE 0x1600
|
||||
#define MC_DC22_VALUE 0x1616
|
||||
#define MC_DC23_VALUE 0x0
|
||||
#define MC_DC24_VALUE 0x5d /* WDQS Tuning for DQS */
|
||||
#define MC_DC25_VALUE 0x0
|
||||
#define MC_DC26_VALUE 0x0
|
||||
#define MC_DC27_VALUE 0x0
|
||||
#define MC_DC28_VALUE 0x514
|
||||
#define MC_DC29_VALUE 0x2d93
|
||||
#define MC_DC30_VALUE 0x8235
|
||||
#define MC_DC31_VALUE 0x0
|
||||
#define MC_DC32_VALUE 0x0
|
||||
#define MC_DC33_VALUE 0x0
|
||||
#define MC_DC34_VALUE 0x0
|
||||
#define MC_DC35_VALUE 0x0
|
||||
#define MC_DC36_VALUE 0x0
|
||||
#define MC_DC37_VALUE 0x0
|
||||
#define MC_DC38_VALUE 0x0
|
||||
#define MC_DC39_VALUE 0x0
|
||||
#define MC_DC40_VALUE 0x0
|
||||
#define MC_DC41_VALUE 0x0
|
||||
#define MC_DC42_VALUE 0x0
|
||||
#define MC_DC43_VALUE 0x0
|
||||
#define MC_DC44_VALUE 0x0
|
||||
#define MC_DC45_VALUE 0x600
|
||||
//#define MC_DC45_VALUE 0x400
|
||||
#define MC_DC46_VALUE 0x0
|
||||
@ -0,0 +1,51 @@
|
||||
/* Settings for Denali DDR SDRAM controller */
|
||||
/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
|
||||
|
||||
#define MC_DC0_VALUE 0x1B1B
|
||||
#define MC_DC1_VALUE 0x0
|
||||
#define MC_DC2_VALUE 0x0
|
||||
#define MC_DC3_VALUE 0x0
|
||||
#define MC_DC4_VALUE 0x0
|
||||
#define MC_DC5_VALUE 0x200
|
||||
#define MC_DC6_VALUE 0x306
|
||||
#define MC_DC7_VALUE 0x303
|
||||
#define MC_DC8_VALUE 0x102
|
||||
#define MC_DC9_VALUE 0x80B
|
||||
#define MC_DC10_VALUE 0x203
|
||||
#define MC_DC11_VALUE 0xD02
|
||||
#define MC_DC12_VALUE 0x1C8
|
||||
#define MC_DC13_VALUE 0x1
|
||||
#define MC_DC14_VALUE 0x0
|
||||
#define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/
|
||||
#define MC_DC16_VALUE 0xC800
|
||||
#define MC_DC17_VALUE 0xF
|
||||
#define MC_DC18_VALUE 0x301
|
||||
#define MC_DC19_VALUE 0x200
|
||||
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
|
||||
#define MC_DC21_VALUE 0x1200
|
||||
#define MC_DC22_VALUE 0x1212
|
||||
#define MC_DC23_VALUE 0x0
|
||||
#define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */
|
||||
#define MC_DC25_VALUE 0x0
|
||||
#define MC_DC26_VALUE 0x0
|
||||
#define MC_DC27_VALUE 0x0
|
||||
#define MC_DC28_VALUE 0x5FB
|
||||
#define MC_DC29_VALUE 0x35DF
|
||||
#define MC_DC30_VALUE 0x99E9
|
||||
#define MC_DC31_VALUE 0x0
|
||||
#define MC_DC32_VALUE 0x0
|
||||
#define MC_DC33_VALUE 0x0
|
||||
#define MC_DC34_VALUE 0x0
|
||||
#define MC_DC35_VALUE 0x0
|
||||
#define MC_DC36_VALUE 0x0
|
||||
#define MC_DC37_VALUE 0x0
|
||||
#define MC_DC38_VALUE 0x0
|
||||
#define MC_DC39_VALUE 0x0
|
||||
#define MC_DC40_VALUE 0x0
|
||||
#define MC_DC41_VALUE 0x0
|
||||
#define MC_DC42_VALUE 0x0
|
||||
#define MC_DC43_VALUE 0x0
|
||||
#define MC_DC44_VALUE 0x0
|
||||
#define MC_DC45_VALUE 0x600
|
||||
//#define MC_DC45_VALUE 0x400
|
||||
#define MC_DC46_VALUE 0x0
|
||||
@ -0,0 +1,51 @@
|
||||
/* Settings for Denali DDR SDRAM controller */
|
||||
/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */
|
||||
|
||||
#define MC_DC0_VALUE 0x1B1B
|
||||
#define MC_DC1_VALUE 0x0
|
||||
#define MC_DC2_VALUE 0x0
|
||||
#define MC_DC3_VALUE 0x0
|
||||
#define MC_DC4_VALUE 0x0
|
||||
#define MC_DC5_VALUE 0x200
|
||||
#define MC_DC6_VALUE 0x306
|
||||
#define MC_DC7_VALUE 0x403
|
||||
#define MC_DC8_VALUE 0x102
|
||||
#define MC_DC9_VALUE 0x90c
|
||||
#define MC_DC10_VALUE 0x203
|
||||
#define MC_DC11_VALUE 0xf02
|
||||
#define MC_DC12_VALUE 0x2c8
|
||||
#define MC_DC13_VALUE 0x1
|
||||
#define MC_DC14_VALUE 0x0
|
||||
#define MC_DC15_VALUE 0x12f /* WDQS tuning for clk_wr*/
|
||||
#define MC_DC16_VALUE 0xc800
|
||||
#define MC_DC17_VALUE 0xf
|
||||
#define MC_DC18_VALUE 0x301
|
||||
#define MC_DC19_VALUE 0x200
|
||||
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
|
||||
#define MC_DC21_VALUE 0x1500
|
||||
#define MC_DC22_VALUE 0x1515
|
||||
#define MC_DC23_VALUE 0x0
|
||||
#define MC_DC24_VALUE 0x57 /* WDQS Tuning for DQS */
|
||||
#define MC_DC25_VALUE 0x0
|
||||
#define MC_DC26_VALUE 0x0
|
||||
#define MC_DC27_VALUE 0x0
|
||||
#define MC_DC28_VALUE 0x6b8
|
||||
#define MC_DC29_VALUE 0x3c84
|
||||
#define MC_DC30_VALUE 0xace5
|
||||
#define MC_DC31_VALUE 0x0
|
||||
#define MC_DC32_VALUE 0x0
|
||||
#define MC_DC33_VALUE 0x0
|
||||
#define MC_DC34_VALUE 0x0
|
||||
#define MC_DC35_VALUE 0x0
|
||||
#define MC_DC36_VALUE 0x0
|
||||
#define MC_DC37_VALUE 0x0
|
||||
#define MC_DC38_VALUE 0x0
|
||||
#define MC_DC39_VALUE 0x0
|
||||
#define MC_DC40_VALUE 0x0
|
||||
#define MC_DC41_VALUE 0x0
|
||||
#define MC_DC42_VALUE 0x0
|
||||
#define MC_DC43_VALUE 0x0
|
||||
#define MC_DC44_VALUE 0x0
|
||||
#define MC_DC45_VALUE 0x600
|
||||
//#define MC_DC45_VALUE 0x400
|
||||
#define MC_DC46_VALUE 0x0
|
||||
@ -0,0 +1,51 @@
|
||||
/* Settings for Denali DDR SDRAM controller */
|
||||
/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */
|
||||
|
||||
#define MC_DC0_VALUE 0x1B1B
|
||||
#define MC_DC1_VALUE 0x0
|
||||
#define MC_DC2_VALUE 0x0
|
||||
#define MC_DC3_VALUE 0x0
|
||||
#define MC_DC4_VALUE 0x0
|
||||
#define MC_DC5_VALUE 0x200
|
||||
#define MC_DC6_VALUE 0x306
|
||||
#define MC_DC7_VALUE 0x403
|
||||
#define MC_DC8_VALUE 0x103
|
||||
#define MC_DC9_VALUE 0xb0e
|
||||
#define MC_DC10_VALUE 0x204
|
||||
#define MC_DC11_VALUE 0x1102
|
||||
#define MC_DC12_VALUE 0x2c8
|
||||
#define MC_DC13_VALUE 0x1
|
||||
#define MC_DC14_VALUE 0x0
|
||||
#define MC_DC15_VALUE 0x155 /* WDQS tuning for clk_wr*/
|
||||
#define MC_DC16_VALUE 0xc800
|
||||
#define MC_DC17_VALUE 0x13
|
||||
#define MC_DC18_VALUE 0x401
|
||||
#define MC_DC19_VALUE 0x200
|
||||
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
|
||||
#define MC_DC21_VALUE 0xc00
|
||||
#define MC_DC22_VALUE 0xc0c
|
||||
#define MC_DC23_VALUE 0x0
|
||||
#define MC_DC24_VALUE 0x74 /* WDQS Tuning for DQS */
|
||||
#define MC_DC25_VALUE 0x0
|
||||
#define MC_DC26_VALUE 0x0
|
||||
#define MC_DC27_VALUE 0x0
|
||||
#define MC_DC28_VALUE 0x798
|
||||
#define MC_DC29_VALUE 0x445d
|
||||
#define MC_DC30_VALUE 0xc351
|
||||
#define MC_DC31_VALUE 0x0
|
||||
#define MC_DC32_VALUE 0x0
|
||||
#define MC_DC33_VALUE 0x0
|
||||
#define MC_DC34_VALUE 0x0
|
||||
#define MC_DC35_VALUE 0x0
|
||||
#define MC_DC36_VALUE 0x0
|
||||
#define MC_DC37_VALUE 0x0
|
||||
#define MC_DC38_VALUE 0x0
|
||||
#define MC_DC39_VALUE 0x0
|
||||
#define MC_DC40_VALUE 0x0
|
||||
#define MC_DC41_VALUE 0x0
|
||||
#define MC_DC42_VALUE 0x0
|
||||
#define MC_DC43_VALUE 0x0
|
||||
#define MC_DC44_VALUE 0x0
|
||||
#define MC_DC45_VALUE 0x600
|
||||
//#define MC_DC45_VALUE 0x400
|
||||
#define MC_DC46_VALUE 0x0
|
||||
@ -0,0 +1,60 @@
|
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Danube board with MIPS 24Kc CPU core
|
||||
#
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
ifdef CONFIG_LZMA_BOOTSTRAP
|
||||
|
||||
ifdef BUILD_BOOTSTRAP
|
||||
|
||||
$(info BUILD_BOOTSTRAP )
|
||||
#TEXT_BASE = 0xB0000000
|
||||
TEXT_BASE = 0x80010000
|
||||
|
||||
else # BUILD_BOOTSTRAP
|
||||
|
||||
ifndef TEXT_BASE
|
||||
$(info redefine TEXT_BASE = 0x80040000 )
|
||||
TEXT_BASE = 0x80040000
|
||||
endif
|
||||
|
||||
endif # BUILD_BOOTSTRAP
|
||||
|
||||
else
|
||||
|
||||
ifdef BUILD_BOOTSTRAP
|
||||
$(error BUILD_BOOTSTRAP but not enabled in config)
|
||||
endif
|
||||
|
||||
ifndef TEXT_BASE
|
||||
## Standard: boot from ebu
|
||||
$(info redefine TEXT_BASE = 0xB0000000 )
|
||||
TEXT_BASE = 0xB0000000
|
||||
## For testing: boot from RAM
|
||||
# TEXT_BASE = 0x80100000
|
||||
endif
|
||||
|
||||
endif # CONFIG_LZMA_BOOTSTRAP
|
||||
@ -0,0 +1,543 @@
|
||||
/*
|
||||
* Memory sub-system initialization code for AR9 board.
|
||||
*
|
||||
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
|
||||
* Copyright (c) 2005 Andre Messerschmidt Infineon
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
/* History:
|
||||
peng liu May 25, 2006, for PLL setting after reset, 05252006
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
#if defined(CONFIG_USE_DDR_RAM)
|
||||
|
||||
#if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M)
|
||||
# include "ar9_ddr111_settings.h"
|
||||
#elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M)
|
||||
# include "ar9_ddr166_settings.h"
|
||||
#elif defined(CONFIG_CPU_442M_RAM_147M)
|
||||
# include "ar9_ddr166_settings.h"
|
||||
#elif defined(CONFIG_CPU_393M_RAM_196M)
|
||||
# ifdef CONFIG_ETRON_RAM
|
||||
# include "etron_ddr196_settings.h"
|
||||
# else
|
||||
# include "ar9_ddr196_settings.h"
|
||||
# endif
|
||||
#elif defined(CONFIG_CPU_442M_RAM_221M)
|
||||
# include "ar9_ddr221_settings.h"
|
||||
#elif defined(CONFIG_CPU_500M_RAM_250M)
|
||||
# include "ar9_ddr250_settings.h"
|
||||
#else
|
||||
# warning "missing definition for ddr_settings.h, use default!"
|
||||
# include "ar9_ddr_settings.h"
|
||||
#endif
|
||||
#endif /* CONFIG_USE_DDR_RAM */
|
||||
|
||||
#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
|
||||
#error "missing include of ddr_settings.h"
|
||||
#endif
|
||||
|
||||
#define EBU_MODUL_BASE 0xBE105300
|
||||
#define EBU_CLC(value) 0x0000(value)
|
||||
#define EBU_CON(value) 0x0010(value)
|
||||
#define EBU_ADDSEL0(value) 0x0020(value)
|
||||
#define EBU_ADDSEL1(value) 0x0024(value)
|
||||
#define EBU_ADDSEL2(value) 0x0028(value)
|
||||
#define EBU_ADDSEL3(value) 0x002C(value)
|
||||
#define EBU_BUSCON0(value) 0x0060(value)
|
||||
#define EBU_BUSCON1(value) 0x0064(value)
|
||||
#define EBU_BUSCON2(value) 0x0068(value)
|
||||
#define EBU_BUSCON3(value) 0x006C(value)
|
||||
|
||||
#define MC_MODUL_BASE 0xBF800000
|
||||
#define MC_ERRCAUSE(value) 0x0010(value)
|
||||
#define MC_ERRADDR(value) 0x0020(value)
|
||||
#define MC_CON(value) 0x0060(value)
|
||||
|
||||
#define MC_SRAM_ENABLE 0x00000004
|
||||
#define MC_SDRAM_ENABLE 0x00000002
|
||||
#define MC_DDRRAM_ENABLE 0x00000001
|
||||
|
||||
#define MC_SDR_MODUL_BASE 0xBF800200
|
||||
#define MC_IOGP(value) 0x0000(value)
|
||||
#define MC_CTRLENA(value) 0x0010(value)
|
||||
#define MC_MRSCODE(value) 0x0020(value)
|
||||
#define MC_CFGDW(value) 0x0030(value)
|
||||
#define MC_CFGPB0(value) 0x0040(value)
|
||||
#define MC_LATENCY(value) 0x0080(value)
|
||||
#define MC_TREFRESH(value) 0x0090(value)
|
||||
#define MC_SELFRFSH(value) 0x00A0(value)
|
||||
|
||||
#define MC_DDR_MODUL_BASE 0xBF801000
|
||||
#define MC_DC00(value) 0x0000(value)
|
||||
#define MC_DC01(value) 0x0010(value)
|
||||
#define MC_DC02(value) 0x0020(value)
|
||||
#define MC_DC03(value) 0x0030(value)
|
||||
#define MC_DC04(value) 0x0040(value)
|
||||
#define MC_DC05(value) 0x0050(value)
|
||||
#define MC_DC06(value) 0x0060(value)
|
||||
#define MC_DC07(value) 0x0070(value)
|
||||
#define MC_DC08(value) 0x0080(value)
|
||||
#define MC_DC09(value) 0x0090(value)
|
||||
#define MC_DC10(value) 0x00A0(value)
|
||||
#define MC_DC11(value) 0x00B0(value)
|
||||
#define MC_DC12(value) 0x00C0(value)
|
||||
#define MC_DC13(value) 0x00D0(value)
|
||||
#define MC_DC14(value) 0x00E0(value)
|
||||
#define MC_DC15(value) 0x00F0(value)
|
||||
#define MC_DC16(value) 0x0100(value)
|
||||
#define MC_DC17(value) 0x0110(value)
|
||||
#define MC_DC18(value) 0x0120(value)
|
||||
#define MC_DC19(value) 0x0130(value)
|
||||
#define MC_DC20(value) 0x0140(value)
|
||||
#define MC_DC21(value) 0x0150(value)
|
||||
#define MC_DC22(value) 0x0160(value)
|
||||
#define MC_DC23(value) 0x0170(value)
|
||||
#define MC_DC24(value) 0x0180(value)
|
||||
#define MC_DC25(value) 0x0190(value)
|
||||
#define MC_DC26(value) 0x01A0(value)
|
||||
#define MC_DC27(value) 0x01B0(value)
|
||||
#define MC_DC28(value) 0x01C0(value)
|
||||
#define MC_DC29(value) 0x01D0(value)
|
||||
#define MC_DC30(value) 0x01E0(value)
|
||||
#define MC_DC31(value) 0x01F0(value)
|
||||
#define MC_DC32(value) 0x0200(value)
|
||||
#define MC_DC33(value) 0x0210(value)
|
||||
#define MC_DC34(value) 0x0220(value)
|
||||
#define MC_DC35(value) 0x0230(value)
|
||||
#define MC_DC36(value) 0x0240(value)
|
||||
#define MC_DC37(value) 0x0250(value)
|
||||
#define MC_DC38(value) 0x0260(value)
|
||||
#define MC_DC39(value) 0x0270(value)
|
||||
#define MC_DC40(value) 0x0280(value)
|
||||
#define MC_DC41(value) 0x0290(value)
|
||||
#define MC_DC42(value) 0x02A0(value)
|
||||
#define MC_DC43(value) 0x02B0(value)
|
||||
#define MC_DC44(value) 0x02C0(value)
|
||||
#define MC_DC45(value) 0x02D0(value)
|
||||
#define MC_DC46(value) 0x02E0(value)
|
||||
|
||||
#define RCU_OFFSET 0xBF203000
|
||||
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
|
||||
#define RCU_STS (RCU_OFFSET + 0x0014)
|
||||
|
||||
#define CGU_OFFSET 0xBF103000
|
||||
#define PLL0_CFG (CGU_OFFSET + 0x0004)
|
||||
#define PLL1_CFG (CGU_OFFSET + 0x0008)
|
||||
#define PLL2_CFG (CGU_OFFSET + 0x000C)
|
||||
#define CGU_SYS (CGU_OFFSET + 0x0010)
|
||||
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
|
||||
#define IF_CLK (CGU_OFFSET + 0x0018)
|
||||
#define CGU_SMD (CGU_OFFSET + 0x0020)
|
||||
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
|
||||
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
|
||||
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
|
||||
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
|
||||
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
|
||||
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
|
||||
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
|
||||
|
||||
#define pll1_36MHz_CONFIG 0x9800f25f
|
||||
|
||||
.set noreorder
|
||||
|
||||
|
||||
/*
|
||||
* void ebu_init(void)
|
||||
*/
|
||||
.globl ebu_init
|
||||
.ent ebu_init
|
||||
ebu_init:
|
||||
|
||||
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
|
||||
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
|
||||
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
|
||||
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
|
||||
|
||||
li t1, EBU_MODUL_BASE
|
||||
#if defined(CONFIG_EBU_ADDSEL0)
|
||||
li t2, CONFIG_EBU_ADDSEL0
|
||||
sw t2, EBU_ADDSEL0(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_ADDSEL1)
|
||||
li t2, CONFIG_EBU_ADDSEL1
|
||||
sw t2, EBU_ADDSEL1(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_ADDSEL2)
|
||||
li t2, CONFIG_EBU_ADDSEL2
|
||||
sw t2, EBU_ADDSEL2(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_ADDSEL3)
|
||||
li t2, CONFIG_EBU_ADDSEL3
|
||||
sw t2, EBU_ADDSEL3(t1)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EBU_BUSCON0)
|
||||
li t2, CONFIG_EBU_BUSCON0
|
||||
sw t2, EBU_BUSCON0(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_BUSCON1)
|
||||
li t2, CONFIG_EBU_BUSCON1
|
||||
sw t2, EBU_BUSCON1(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_BUSCON2)
|
||||
li t2, CONFIG_EBU_BUSCON2
|
||||
sw t2, EBU_BUSCON2(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_BUSCON3)
|
||||
li t2, CONFIG_EBU_BUSCON3
|
||||
sw t2, EBU_BUSCON3(t1)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end ebu_init
|
||||
|
||||
|
||||
/*
|
||||
* void cgu_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl cgu_init
|
||||
.ent cgu_init
|
||||
cgu_init:
|
||||
li t2, CGU_SYS
|
||||
lw t2,0(t2)
|
||||
beq t2,a0,freq_up2date
|
||||
nop
|
||||
li t1, CGU_SYS
|
||||
sw a0,0(t1)
|
||||
|
||||
#if defined(CONFIG_CPU_333M_RAM_166M) && defined(CONFIG_USE_PLL1)
|
||||
li t1, PLL1_CFG
|
||||
li a1, pll1_36MHz_CONFIG
|
||||
sw a1, 0(t1)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CLASS_II_DDR_PAD)
|
||||
li t1, CGU_SMD
|
||||
li a1, 0x200000
|
||||
sw a1, 0(t1) // Turn on DDR PAD Class II to INC drive.
|
||||
#endif
|
||||
|
||||
li t1, RCU_RST_REQ
|
||||
li t2, 0x40000008
|
||||
sw t2,0(t1)
|
||||
b wait_reset
|
||||
nop
|
||||
|
||||
wait_reset:
|
||||
b wait_reset
|
||||
nop
|
||||
|
||||
freq_up2date:
|
||||
j ra
|
||||
nop
|
||||
.end cgu_init
|
||||
|
||||
|
||||
#ifndef CONFIG_USE_DDR_RAM
|
||||
/*
|
||||
* void sdram_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl sdram_init
|
||||
.ent sdram_init
|
||||
sdram_init:
|
||||
|
||||
/* SDRAM Initialization
|
||||
*/
|
||||
li t1, MC_MODUL_BASE
|
||||
|
||||
/* Clear Error log registers */
|
||||
sw zero, MC_ERRCAUSE(t1)
|
||||
sw zero, MC_ERRADDR(t1)
|
||||
|
||||
/* Enable SDRAM module in memory controller */
|
||||
li t3, MC_SDRAM_ENABLE
|
||||
lw t2, MC_CON(t1)
|
||||
or t3, t2, t3
|
||||
sw t3, MC_CON(t1)
|
||||
|
||||
li t1, MC_SDR_MODUL_BASE
|
||||
|
||||
/* disable the controller */
|
||||
li t2, 0
|
||||
sw t2, MC_CTRLENA(t1)
|
||||
|
||||
li t2, 0x822
|
||||
sw t2, MC_IOGP(t1)
|
||||
|
||||
li t2, 0x2
|
||||
sw t2, MC_CFGDW(t1)
|
||||
|
||||
/* Set CAS Latency */
|
||||
li t2, 0x00000020
|
||||
sw t2, MC_MRSCODE(t1)
|
||||
|
||||
/* Set CS0 to SDRAM parameters */
|
||||
li t2, 0x000014d8
|
||||
sw t2, MC_CFGPB0(t1)
|
||||
|
||||
/* Set SDRAM latency parameters */
|
||||
li t2, 0x00036325; /* BC PC100 */
|
||||
sw t2, MC_LATENCY(t1)
|
||||
|
||||
/* Set SDRAM refresh rate */
|
||||
li t2, 0x00000C30
|
||||
sw t2, MC_TREFRESH(t1)
|
||||
|
||||
/* Clear Power-down registers */
|
||||
sw zero, MC_SELFRFSH(t1)
|
||||
|
||||
/* Finally enable the controller */
|
||||
li t2, 1
|
||||
sw t2, MC_CTRLENA(t1)
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end sdram_init
|
||||
|
||||
#endif /* !CONFIG_USE_DDR_RAM */
|
||||
|
||||
#ifdef CONFIG_USE_DDR_RAM
|
||||
/*
|
||||
* void ddrram_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl ddrram_init
|
||||
.ent ddrram_init
|
||||
ddrram_init:
|
||||
|
||||
/* DDR-DRAM Initialization
|
||||
*/
|
||||
li t1, MC_MODUL_BASE
|
||||
|
||||
/* Clear Error log registers */
|
||||
sw zero, MC_ERRCAUSE(t1)
|
||||
sw zero, MC_ERRADDR(t1)
|
||||
|
||||
/* Enable DDR module in memory controller */
|
||||
li t3, MC_DDRRAM_ENABLE
|
||||
lw t2, MC_CON(t1)
|
||||
or t3, t2, t3
|
||||
sw t3, MC_CON(t1)
|
||||
|
||||
li t1, MC_DDR_MODUL_BASE
|
||||
|
||||
/* Write configuration to DDR controller registers */
|
||||
li t2, MC_DC0_VALUE
|
||||
sw t2, MC_DC00(t1)
|
||||
|
||||
li t2, MC_DC1_VALUE
|
||||
sw t2, MC_DC01(t1)
|
||||
|
||||
li t2, MC_DC2_VALUE
|
||||
sw t2, MC_DC02(t1)
|
||||
|
||||
li t2, MC_DC3_VALUE
|
||||
sw t2, MC_DC03(t1)
|
||||
|
||||
li t2, MC_DC4_VALUE
|
||||
sw t2, MC_DC04(t1)
|
||||
|
||||
li t2, MC_DC5_VALUE
|
||||
sw t2, MC_DC05(t1)
|
||||
|
||||
li t2, MC_DC6_VALUE
|
||||
sw t2, MC_DC06(t1)
|
||||
|
||||
li t2, MC_DC7_VALUE
|
||||
sw t2, MC_DC07(t1)
|
||||
|
||||
li t2, MC_DC8_VALUE
|
||||
sw t2, MC_DC08(t1)
|
||||
|
||||
li t2, MC_DC9_VALUE
|
||||
sw t2, MC_DC09(t1)
|
||||
|
||||
li t2, MC_DC10_VALUE
|
||||
sw t2, MC_DC10(t1)
|
||||
|
||||
li t2, MC_DC11_VALUE
|
||||
sw t2, MC_DC11(t1)
|
||||
|
||||
li t2, MC_DC12_VALUE
|
||||
sw t2, MC_DC12(t1)
|
||||
|
||||
li t2, MC_DC13_VALUE
|
||||
sw t2, MC_DC13(t1)
|
||||
|
||||
li t2, MC_DC14_VALUE
|
||||
sw t2, MC_DC14(t1)
|
||||
|
||||
li t2, MC_DC15_VALUE
|
||||
sw t2, MC_DC15(t1)
|
||||
|
||||
li t2, MC_DC16_VALUE
|
||||
sw t2, MC_DC16(t1)
|
||||
|
||||
li t2, MC_DC17_VALUE
|
||||
sw t2, MC_DC17(t1)
|
||||
|
||||
li t2, MC_DC18_VALUE
|
||||
sw t2, MC_DC18(t1)
|
||||
|
||||
li t2, MC_DC19_VALUE
|
||||
sw t2, MC_DC19(t1)
|
||||
|
||||
li t2, MC_DC20_VALUE
|
||||
sw t2, MC_DC20(t1)
|
||||
|
||||
li t2, MC_DC21_VALUE
|
||||
sw t2, MC_DC21(t1)
|
||||
|
||||
li t2, MC_DC22_VALUE
|
||||
sw t2, MC_DC22(t1)
|
||||
|
||||
li t2, MC_DC23_VALUE
|
||||
sw t2, MC_DC23(t1)
|
||||
|
||||
li t2, MC_DC24_VALUE
|
||||
sw t2, MC_DC24(t1)
|
||||
|
||||
li t2, MC_DC25_VALUE
|
||||
sw t2, MC_DC25(t1)
|
||||
|
||||
li t2, MC_DC26_VALUE
|
||||
sw t2, MC_DC26(t1)
|
||||
|
||||
li t2, MC_DC27_VALUE
|
||||
sw t2, MC_DC27(t1)
|
||||
|
||||
li t2, MC_DC28_VALUE
|
||||
sw t2, MC_DC28(t1)
|
||||
|
||||
li t2, MC_DC29_VALUE
|
||||
sw t2, MC_DC29(t1)
|
||||
|
||||
li t2, MC_DC30_VALUE
|
||||
sw t2, MC_DC30(t1)
|
||||
|
||||
li t2, MC_DC31_VALUE
|
||||
sw t2, MC_DC31(t1)
|
||||
|
||||
li t2, MC_DC32_VALUE
|
||||
sw t2, MC_DC32(t1)
|
||||
|
||||
li t2, MC_DC33_VALUE
|
||||
sw t2, MC_DC33(t1)
|
||||
|
||||
li t2, MC_DC34_VALUE
|
||||
sw t2, MC_DC34(t1)
|
||||
|
||||
li t2, MC_DC35_VALUE
|
||||
sw t2, MC_DC35(t1)
|
||||
|
||||
li t2, MC_DC36_VALUE
|
||||
sw t2, MC_DC36(t1)
|
||||
|
||||
li t2, MC_DC37_VALUE
|
||||
sw t2, MC_DC37(t1)
|
||||
|
||||
li t2, MC_DC38_VALUE
|
||||
sw t2, MC_DC38(t1)
|
||||
|
||||
li t2, MC_DC39_VALUE
|
||||
sw t2, MC_DC39(t1)
|
||||
|
||||
li t2, MC_DC40_VALUE
|
||||
sw t2, MC_DC40(t1)
|
||||
|
||||
li t2, MC_DC41_VALUE
|
||||
sw t2, MC_DC41(t1)
|
||||
|
||||
li t2, MC_DC42_VALUE
|
||||
sw t2, MC_DC42(t1)
|
||||
|
||||
li t2, MC_DC43_VALUE
|
||||
sw t2, MC_DC43(t1)
|
||||
|
||||
li t2, MC_DC44_VALUE
|
||||
sw t2, MC_DC44(t1)
|
||||
|
||||
li t2, MC_DC45_VALUE
|
||||
sw t2, MC_DC45(t1)
|
||||
|
||||
li t2, MC_DC46_VALUE
|
||||
sw t2, MC_DC46(t1)
|
||||
|
||||
li t2, 0x00000100
|
||||
sw t2, MC_DC03(t1)
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end ddrram_init
|
||||
#endif /* CONFIG_USE_DDR_RAM */
|
||||
|
||||
.globl lowlevel_init
|
||||
.ent lowlevel_init
|
||||
lowlevel_init:
|
||||
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
|
||||
*/
|
||||
move t0, ra
|
||||
/* We rely on the fact that non of the following ..._init() functions
|
||||
* modify t0
|
||||
*/
|
||||
#if defined(CONFIG_SYS_EBU_BOOT)
|
||||
/*
|
||||
using PPL1 value
|
||||
*/
|
||||
li a0,0x90
|
||||
bal cgu_init
|
||||
nop
|
||||
#endif /* CONFIG_SYS_EBU_BOOT */
|
||||
|
||||
bal ebu_init
|
||||
nop
|
||||
|
||||
#ifdef CONFIG_SYS_EBU_BOOT
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
#ifdef CONFIG_USE_DDR_RAM
|
||||
bal ddrram_init
|
||||
nop
|
||||
#else
|
||||
bal sdram_init
|
||||
nop
|
||||
#endif
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
#endif /* CONFIG_SYS_EBU_BOOT */
|
||||
|
||||
move ra, t0
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end lowlevel_init
|
||||
@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Power Management unit initialization code for AMAZON development board.
|
||||
*
|
||||
* Copyright (c) 2003 Ou Ke, Infineon.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
#define PMU_PWDCR 0xBF10201C
|
||||
#define PMU_SR 0xBF102020
|
||||
|
||||
.globl pmuenable
|
||||
|
||||
pmuenable:
|
||||
li t0, PMU_PWDCR
|
||||
li t1, 0x2 /* enable everything */
|
||||
sw t1, 0(t0)
|
||||
#if 0
|
||||
1:
|
||||
li t0, PMU_SR
|
||||
lw t2, 0(t0)
|
||||
bne t1, t2, 1b
|
||||
nop
|
||||
#endif
|
||||
j ra
|
||||
nop
|
||||
|
||||
|
||||
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk Engineering, <wd@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
|
||||
*/
|
||||
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
|
||||
.got : {
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
*(.u_boot_cmd)
|
||||
__u_boot_cmd_end = .;
|
||||
}
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss (NOLOAD) : { *(.sbss) }
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
uboot_end = .;
|
||||
}
|
||||
@ -0,0 +1,46 @@
|
||||
#########################################################################
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(SOC).a
|
||||
|
||||
COBJS = clock.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
||||
all: $(obj).depend $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,67 @@
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ar9.h>
|
||||
|
||||
ulong ifx_get_ddr_hz(void)
|
||||
{
|
||||
switch((*AR9_CGU_SYS) & 0x05) {
|
||||
case 0x01:
|
||||
case 0x05:
|
||||
return CLOCK_111M;
|
||||
|
||||
case 0x00:
|
||||
case 0x04:
|
||||
return CLOCK_166M;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
ulong ifx_get_cpuclk(void)
|
||||
{
|
||||
switch((*AR9_CGU_SYS) & 0x05) {
|
||||
case 0x00:
|
||||
case 0x01:
|
||||
return CLOCK_333M;
|
||||
|
||||
case 0x04:
|
||||
return CLOCK_166M;
|
||||
|
||||
case 0x05:
|
||||
return CLOCK_111M;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
ulong get_bus_freq(ulong dummy)
|
||||
{
|
||||
unsigned int ddr_clock=ifx_get_ddr_hz();
|
||||
if((*AR9_CGU_SYS) & 0x40){
|
||||
return ddr_clock/2;
|
||||
} else {
|
||||
return ddr_clock;
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,60 @@
|
||||
|
||||
#define IFX_CACHE_EXTRA_INVALID_TAG \
|
||||
mtc0 zero, CP0_TAGLO, 1; \
|
||||
mtc0 zero, CP0_TAGLO, 2; \
|
||||
mtc0 zero, CP0_TAGLO, 3; \
|
||||
mtc0 zero, CP0_TAGLO, 4;
|
||||
|
||||
#define IFX_CACHE_EXTRA_OPERATION \
|
||||
/* set WST bit */ \
|
||||
mfc0 a0, CP0_ECC; \
|
||||
li a1, ECCF_WST; \
|
||||
or a0, a1; \
|
||||
mtc0 a0, CP0_ECC; \
|
||||
\
|
||||
li a0, K0BASE; \
|
||||
move a2, t2; /* icacheSize */ \
|
||||
move a3, t4; /* icacheLineSize */ \
|
||||
move a1, a2; \
|
||||
icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \
|
||||
\
|
||||
/* clear WST bit */ \
|
||||
mfc0 a0, CP0_ECC; \
|
||||
li a1, ~ECCF_WST; \
|
||||
and a0, a1; \
|
||||
mtc0 a0, CP0_ECC; \
|
||||
\
|
||||
/* 1: initialise dcache tags. */ \
|
||||
\
|
||||
/* cache line size */ \
|
||||
li a2, CFG_CACHELINE_SIZE; \
|
||||
/* kseg0 mem address */ \
|
||||
li a1, 0; \
|
||||
li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \
|
||||
1: \
|
||||
/* store tag (invalid, not locked) */ \
|
||||
cache 0x8, 0(a1); \
|
||||
cache 0x9, 0(a1); \
|
||||
\
|
||||
add a3, -1; \
|
||||
bne a3, zero, 1b; \
|
||||
add a1, a2; \
|
||||
\
|
||||
/* set WST bit */ \
|
||||
mfc0 a0, CP0_ECC; \
|
||||
li a1, ECCF_WST; \
|
||||
or a0, a1; \
|
||||
mtc0 a0, CP0_ECC; \
|
||||
\
|
||||
li a0, K0BASE; \
|
||||
move a2, t3; /* dcacheSize */ \
|
||||
move a3, t5; /* dcacheLineSize */ \
|
||||
move a1, a2; \
|
||||
icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \
|
||||
\
|
||||
/* clear WST bit */ \
|
||||
mfc0 a0, CP0_ECC; \
|
||||
li a1, ~ECCF_WST; \
|
||||
and a0, a1; \
|
||||
mtc0 a0, CP0_ECC;
|
||||
|
||||
@ -0,0 +1,424 @@
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Ralph Hempel
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : PMU register address and bits */
|
||||
/***********************************************************************/
|
||||
#define AR9_PMU (0xBF102000)
|
||||
/* PMU Power down Control Register */
|
||||
#define AR9_PMU_PWDCR ((volatile u32*)(AR9_PMU + 0x001C))
|
||||
/* PMU Status Register */
|
||||
#define AR9_PMU_SR ((volatile u32*)(AR9_PMU + 0x0020))
|
||||
/** DMA block */
|
||||
#define AR9_PMU_DMA (1<<5)
|
||||
#define AR9_PMU_SDIO (1<<16)
|
||||
#define AR9_PMU_USB0 (1<<6)
|
||||
#define AR9_PMU_USB0_P (1<<0)
|
||||
#define AR9_PMU_SWITCH (1<<28)
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : RCU register address and bits */
|
||||
/***********************************************************************/
|
||||
#define AR9_RCU_BASE_ADDR (0xBF203000)
|
||||
#define AR9_RCU_RST_REQ ((volatile u32*)(AR9_RCU_BASE_ADDR + 0x0010))
|
||||
#define AR9_RCU_RST_STAT ((volatile u32*)(AR9_RCU_BASE_ADDR + 0x0014))
|
||||
#define AR9_RST_ALL (1 << 30)
|
||||
|
||||
/*** Reset Request Register Bits ***/
|
||||
#define AR9_RCU_RST_REQ_SRST (1 << 30)
|
||||
#define AR9_RCU_RST_REQ_ARC_JTAG (1 << 20)
|
||||
#define AR9_RCU_RST_REQ_PCI (1 << 13)
|
||||
#define AR9_RCU_RST_REQ_AFE (1 << 11)
|
||||
#define AR9_RCU_RST_REQ_SDIO (1 << 19)
|
||||
#define AR9_RCU_RST_REQ_DMA (1 << 9)
|
||||
#define AR9_RCU_RST_REQ_PPE (1 << 8)
|
||||
#define AR9_RCU_RST_REQ_DFE (1 << 7)
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : GPIO register address and bits */
|
||||
/***********************************************************************/
|
||||
#define AR9_GPIO (0xBE100B00)
|
||||
/***Port 0 Data Output Register (0010H)***/
|
||||
#define AR9_GPIO_P0_OUT ((volatile u32 *)(AR9_GPIO+ 0x0010))
|
||||
/***Port 1 Data Output Register (0040H)***/
|
||||
#define AR9_GPIO_P1_OUT ((volatile u32 *)(AR9_GPIO+ 0x0040))
|
||||
/***Port 2 Data Output Register (0070H)***/
|
||||
#define AR9_GPIO_P2_OUT ((volatile u32 *)(AR9_GPIO+ 0x0070))
|
||||
/***Port 3 Data Output Register (00A0H)***/
|
||||
#define AR9_GPIO_P3_OUT ((volatile u32 *)(AR9_GPIO+ 0x00A0))
|
||||
/***Port 0 Data Input Register (0014H)***/
|
||||
#define AR9_GPIO_P0_IN ((volatile u32 *)(AR9_GPIO+ 0x0014))
|
||||
/***Port 1 Data Input Register (0044H)***/
|
||||
#define AR9_GPIO_P1_IN ((volatile u32 *)(AR9_GPIO+ 0x0044))
|
||||
/***Port 2 Data Input Register (0074H)***/
|
||||
#define AR9_GPIO_P2_IN ((volatile u32 *)(AR9_GPIO+ 0x0074))
|
||||
/***Port 3 Data Input Register (00A4H)***/
|
||||
#define AR9_GPIO_P3_IN ((volatile u32 *)(AR9_GPIO+ 0x00A4))
|
||||
/***Port 0 Direction Register (0018H)***/
|
||||
#define AR9_GPIO_P0_DIR ((volatile u32 *)(AR9_GPIO+ 0x0018))
|
||||
/***Port 1 Direction Register (0048H)***/
|
||||
#define AR9_GPIO_P1_DIR ((volatile u32 *)(AR9_GPIO+ 0x0048))
|
||||
/***Port 2 Direction Register (0078H)***/
|
||||
#define AR9_GPIO_P2_DIR ((volatile u32 *)(AR9_GPIO+ 0x0078))
|
||||
/***Port 3 Direction Register (0048H)***/
|
||||
#define AR9_GPIO_P3_DIR ((volatile u32 *)(AR9_GPIO+ 0x00A8))
|
||||
/***Port 0 Alternate Function Select Register 0 (001C H) ***/
|
||||
#define AR9_GPIO_P0_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x001C))
|
||||
/***Port 1 Alternate Function Select Register 0 (004C H) ***/
|
||||
#define AR9_GPIO_P1_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x004C))
|
||||
/***Port 2 Alternate Function Select Register 0 (007C H) ***/
|
||||
#define AR9_GPIO_P2_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x007C))
|
||||
/***Port 3 Alternate Function Select Register 0 (00AC H) ***/
|
||||
#define AR9_GPIO_P3_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x00AC))
|
||||
/***Port 0 Alternate Function Select Register 1 (0020 H) ***/
|
||||
#define AR9_GPIO_P0_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0020))
|
||||
/***Port 1 Alternate Function Select Register 0 (0050 H) ***/
|
||||
#define AR9_GPIO_P1_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0050))
|
||||
/***Port 2 Alternate Function Select Register 0 (0080 H) ***/
|
||||
#define AR9_GPIO_P2_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0080))
|
||||
/***Port 3 Alternate Function Select Register 0 (0064 H) ***/
|
||||
#define AR9_GPIO_P3_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0064))
|
||||
/***Port 0 Open Drain Control Register (0024H)***/
|
||||
#define AR9_GPIO_P0_OD ((volatile u32 *)(AR9_GPIO+ 0x0024))
|
||||
/***Port 1 Open Drain Control Register (0054H)***/
|
||||
#define AR9_GPIO_P1_OD ((volatile u32 *)(AR9_GPIO+ 0x0054))
|
||||
/***Port 2 Open Drain Control Register (0084H)***/
|
||||
#define AR9_GPIO_P2_OD ((volatile u32 *)(AR9_GPIO+ 0x0084))
|
||||
/***Port 3 Open Drain Control Register (0034H)***/
|
||||
#define AR9_GPIO_P3_OD ((volatile u32 *)(AR9_GPIO+ 0x0034))
|
||||
/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
|
||||
#define AR9_GPIO_P0_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0028))
|
||||
/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
|
||||
#define AR9_GPIO_P1_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0058))
|
||||
/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/
|
||||
#define AR9_GPIO_P2_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0088))
|
||||
/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/
|
||||
//#define AR9_GPIO_P3_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0094))
|
||||
/***Port 0 Pull Up/Pull Down Select Register (002C H)***/
|
||||
#define AR9_GPIO_P0_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x002C))
|
||||
/***Port 1 Pull Up/Pull Down Select Register (005C H)***/
|
||||
#define AR9_GPIO_P1_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x005C))
|
||||
/***Port 2 Pull Up/Pull Down Select Register (008C H)***/
|
||||
#define AR9_GPIO_P2_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x008C))
|
||||
/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/
|
||||
#define AR9_GPIO_P3_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x0038))
|
||||
/***Port 0 Pull Up Device Enable Register (0030 H)***/
|
||||
#define AR9_GPIO_P0_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0030))
|
||||
/***Port 1 Pull Up Device Enable Register (0060 H)***/
|
||||
#define AR9_GPIO_P1_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0060))
|
||||
/***Port 2 Pull Up Device Enable Register (0090 H)***/
|
||||
#define AR9_GPIO_P2_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0090))
|
||||
/***Port 3 Pull Up Device Enable Register (003c H)***/
|
||||
#define AR9_GPIO_P3_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x003C))
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : CGU register address and bits */
|
||||
/***********************************************************************/
|
||||
#define AR9_CGU (0xBF103000)
|
||||
/***CGU Clock PLL0 ***/
|
||||
#define AR9_CGU_PLL0_CFG ((volatile u32*)(AR9_CGU+ 0x0004))
|
||||
/***CGU Clock PLL1 ***/
|
||||
#define AR9_CGU_PLL1_CFG ((volatile u32*)(AR9_CGU+ 0x0008))
|
||||
/***CGU Clock SYS Mux Register***/
|
||||
#define AR9_CGU_SYS ((volatile u32*)(AR9_CGU+ 0x0010))
|
||||
/***CGU Interface Clock Control Register***/
|
||||
#define AR9_CGU_IFCCR ((volatile u32*)(AR9_CGU+ 0x0018))
|
||||
/***CGU PCI Clock Control Register**/
|
||||
#define AR9_CGU_PCICR ((volatile u32*)(AR9_CGU+ 0x0034))
|
||||
#define CLOCK_60M 60000000
|
||||
#define CLOCK_83M 83333333
|
||||
#define CLOCK_111M 111111111
|
||||
#define CLOCK_133M 133333333
|
||||
#define CLOCK_166M 166666667
|
||||
#define CLOCK_196M 196666667
|
||||
#define CLOCK_333M 333333333
|
||||
#define CLOCK_366M 366666667
|
||||
#define CLOCK_500M 500000000
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : MPS register address and bits */
|
||||
/***********************************************************************/
|
||||
#define AR9_MPS (KSEG1+0x1F107000)
|
||||
#define AR9_MPS_CHIPID ((volatile u32*)(AR9_MPS + 0x0344))
|
||||
#define AR9_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
|
||||
#define AR9_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
|
||||
#define AR9_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : EBU register address and bits */
|
||||
/***********************************************************************/
|
||||
#define AR9_EBU (0xBE105300)
|
||||
|
||||
#define AR9_EBU_CLC ((volatile u32*)(AR9_EBU+ 0x0000))
|
||||
#define AR9_EBU_CLC_DISS (1 << 1)
|
||||
#define AR9_EBU_CLC_DISR (1 << 0)
|
||||
|
||||
#define AR9_EBU_ID ((volatile u32*)(AR9_EBU+ 0x0008))
|
||||
|
||||
/***EBU Global Control Register***/
|
||||
#define AR9_EBU_CON ((volatile u32*)(AR9_EBU+ 0x0010))
|
||||
#define AR9_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20)
|
||||
#define AR9_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16)
|
||||
#define AR9_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8)
|
||||
#define AR9_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6)
|
||||
#define AR9_EBU_CON_ARBSYNC (1 << 5)
|
||||
//#define AR9_EBU_CON_1 (1 << 3)
|
||||
|
||||
/***EBU Address Select Register 0***/
|
||||
#define AR9_EBU_ADDSEL0 ((volatile u32*)(AR9_EBU + 0x0020))
|
||||
/***EBU Address Select Register 1***/
|
||||
#define AR9_EBU_ADDSEL1 ((volatile u32*)(AR9_EBU + 0x0024))
|
||||
/***EBU Address Select Register 2***/
|
||||
#define AR9_EBU_ADDSEL2 ((volatile u32*)(AR9_EBU + 0x0028))
|
||||
/***EBU Address Select Register 3***/
|
||||
#define AR9_EBU_ADDSEL3 ((volatile u32*)(AR9_EBU + 0x002C))
|
||||
#define AR9_EBU_ADDSEL_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
|
||||
#define AR9_EBU_ADDSEL_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
|
||||
#define AR9_EBU_ADDSEL_MIRRORE (1 << 1)
|
||||
#define AR9_EBU_ADDSEL_REGEN (1 << 0)
|
||||
|
||||
/***EBU Bus Configuration Register 0***/
|
||||
#define AR9_EBU_BUSCON0 ((volatile u32*)(AR9_EBU+ 0x0060))
|
||||
#define AR9_EBU_BUSCON0_WRDIS (1 << 31)
|
||||
#define AR9_EBU_BUSCON0_ADSWP (value) (1 << 30)
|
||||
#define AR9_EBU_BUSCON0_PG_EN (value) (1 << 29)
|
||||
#define AR9_EBU_BUSCON0_AGEN (value) (((( 1 << 3) - 1) & (value)) << 24)
|
||||
#define AR9_EBU_BUSCON0_SETUP (1 << 22)
|
||||
#define AR9_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
|
||||
#define AR9_EBU_BUSCON0_WAITINV (1 << 19)
|
||||
#define AR9_EBU_BUSCON0_VN_EN (1 << 18)
|
||||
#define AR9_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
|
||||
#define AR9_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 14)
|
||||
#define AR9_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 12)
|
||||
#define AR9_EBU_BUSCON0_WAITWDC (value) (((( 1 << 4) - 1) & (value)) << 8)
|
||||
#define AR9_EBU_BUSCON0_WAITRRC (value) (((( 1 << 2) - 1) & (value)) << 6)
|
||||
#define AR9_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
|
||||
#define AR9_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
|
||||
#define AR9_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
|
||||
|
||||
/***EBU Bus Configuration Register 1***/
|
||||
#define AR9_EBU_BUSCON1 ((volatile u32*)(AR9_EBU+ 0x0064))
|
||||
#define AR9_EBU_BUSCON1_WRDIS (1 << 31)
|
||||
#define AR9_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
|
||||
#define AR9_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
|
||||
#define AR9_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
|
||||
#define AR9_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
|
||||
#define AR9_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
|
||||
#define AR9_EBU_BUSCON1_WAITINV (1 << 19)
|
||||
#define AR9_EBU_BUSCON1_SETUP (1 << 18)
|
||||
#define AR9_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
|
||||
#define AR9_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
|
||||
#define AR9_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
|
||||
#define AR9_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
|
||||
#define AR9_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
|
||||
#define AR9_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
|
||||
|
||||
/***EBU Bus Configuration Register 2***/
|
||||
#define AR9_EBU_BUSCON2 ((volatile u32*)(AR9_EBU+ 0x0068))
|
||||
#define AR9_EBU_BUSCON2_WRDIS (1 << 31)
|
||||
#define AR9_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
|
||||
#define AR9_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
|
||||
#define AR9_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
|
||||
#define AR9_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
|
||||
#define AR9_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
|
||||
#define AR9_EBU_BUSCON2_WAITINV (1 << 19)
|
||||
#define AR9_EBU_BUSCON2_SETUP (1 << 18)
|
||||
#define AR9_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
|
||||
#define AR9_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
|
||||
#define AR9_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
|
||||
#define AR9_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
|
||||
#define AR9_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
|
||||
#define AR9_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
|
||||
|
||||
/***EBU Bus Configuration Register 2***/
|
||||
#define AR9_EBU_BUSCON3 ((volatile u32*)(AR9_EBU+ 0x006C))
|
||||
#define AR9_EBU_BUSCON3_WRDIS (1 << 31)
|
||||
#define AR9_EBU_BUSCON3_ADSWP (value) (1 << 30)
|
||||
#define AR9_EBU_BUSCON3_PG_EN (value) (1 << 29)
|
||||
#define AR9_EBU_BUSCON3_AGEN (value) (((( 1 << 3) - 1) & (value)) << 24)
|
||||
#define AR9_EBU_BUSCON3_SETUP (1 << 22)
|
||||
#define AR9_EBU_BUSCON3_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
|
||||
#define AR9_EBU_BUSCON3_WAITINV (1 << 19)
|
||||
#define AR9_EBU_BUSCON3_VN_EN (1 << 18)
|
||||
#define AR9_EBU_BUSCON3_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
|
||||
#define AR9_EBU_BUSCON3_ALEC (value) (((( 1 << 2) - 1) & (value)) << 14)
|
||||
#define AR9_EBU_BUSCON3_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 12)
|
||||
#define AR9_EBU_BUSCON3_WAITWDC (value) (((( 1 << 4) - 1) & (value)) << 8)
|
||||
#define AR9_EBU_BUSCON3_WAITRRC (value) (((( 1 << 2) - 1) & (value)) << 6)
|
||||
#define AR9_EBU_BUSCON3_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
|
||||
#define AR9_EBU_BUSCON3_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
|
||||
#define AR9_EBU_BUSCON3_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : SDRAM register address and bits */
|
||||
/***********************************************************************/
|
||||
#define AR9_SDRAM (0xBF800000)
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : ASC0 register address and bits */
|
||||
/***********************************************************************/
|
||||
#define AR9_ASC0 (KSEG1 | 0x1E100400)
|
||||
#define AR9_ASC0_TBUF ((volatile u32*)(AR9_ASC0 + 0x0020))
|
||||
#define AR9_ASC0_RBUF ((volatile u32*)(AR9_ASC0 + 0x0024))
|
||||
#define AR9_ASC0_FSTAT ((volatile u32*)(AR9_ASC0 + 0x0048))
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : ASC1 register address and bits */
|
||||
/***********************************************************************/
|
||||
#define AR9_ASC1 (KSEG1 | 0x1E100C00)
|
||||
#define AR9_ASC1_TBUF ((volatile u32*)(AR9_ASC1 + 0x0020))
|
||||
#define AR9_ASC1_RBUF ((volatile u32*)(AR9_ASC1 + 0x0024))
|
||||
#define AR9_ASC1_FSTAT ((volatile u32*)(AR9_ASC1 + 0x0048))
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : DMA register address and bits */
|
||||
/***********************************************************************/
|
||||
#define AR9_DMA_OFFSET (0xBE104100)
|
||||
/***********************************************************************/
|
||||
#define AR9_DMA_CLC ((volatile u32*)(AR9_DMA_OFFSET + 0x0000))
|
||||
#define AR9_DMA_ID ((volatile u32*)(AR9_DMA_OFFSET + 0x0008))
|
||||
#define AR9_DMA_CTRL (volatile u32*)(AR9_DMA_BASE + 0x10)
|
||||
|
||||
/** DMA Port Select Register */
|
||||
#define AR9_DMA_PS ((volatile u32*)(AR9_DMA_OFFSET + 0x0040))
|
||||
/** DMA Port Control Register */
|
||||
#define AR9_DMA_PCTRL ((volatile u32*)(AR9_DMA_OFFSET + 0x0044))
|
||||
#define AR9_DMA_IRNEN ((volatile u32*)(AR9_DMA_OFFSET + 0x00F4))
|
||||
#define AR9_DMA_IRNCR ((volatile u32*)(AR9_DMA_OFFSET + 0x00F8))
|
||||
#define AR9_DMA_IRNICR ((volatile u32*)(AR9_DMA_OFFSET + 0x00FC))
|
||||
|
||||
#define AR9_DMA_CS ((volatile u32*)(AR9_DMA_OFFSET + 0x0018))
|
||||
#define AR9_DMA_CCTRL ((volatile u32*)(AR9_DMA_OFFSET + 0x001C))
|
||||
#define AR9_DMA_CDBA ((volatile u32*)(AR9_DMA_OFFSET + 0x0020))
|
||||
#define AR9_DMA_CIE ((volatile u32*)(AR9_DMA_OFFSET + 0x002C))
|
||||
#define AR9_DMA_CIS ((volatile u32*)(AR9_DMA_OFFSET + 0x0028))
|
||||
#define AR9_DMA_CDLEN ((volatile u32*)(AR9_DMA_OFFSET + 0x0024))
|
||||
#define AR9_DMA_CPOLL ((volatile u32*)(AR9_DMA_OFFSET + 0x0014))
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : GPORT switch register */
|
||||
/***********************************************************************/
|
||||
#define AR9_SW (0xBE108000)
|
||||
#define AR9_SW_PS (AR9_SW + 0x000)
|
||||
#define AR9_SW_P0_CTL (AR9_SW + 0x004)
|
||||
#define AR9_SW_P1_CTL (AR9_SW + 0x008)
|
||||
#define AR9_SW_P2_CTL (AR9_SW + 0x00C)
|
||||
#define AR9_SW_P0_VLAN (AR9_SW + 0x010)
|
||||
#define AR9_SW_P1_VLAN (AR9_SW + 0x014)
|
||||
#define AR9_SW_P2_VLAN (AR9_SW + 0x018)
|
||||
#define AR9_SW_P0_INCTL (AR9_SW + 0x020)
|
||||
#define AR9_SW_P1_INCTL (AR9_SW + 0x024)
|
||||
#define AR9_SW_P2_INCTL (AR9_SW + 0x028)
|
||||
#define AR9_SW_DF_PORTMAP (AR9_SW + 0x02C)
|
||||
#define AR9_SW_P0_ECS_Q32 (AR9_SW + 0x030)
|
||||
#define AR9_SW_P0_ECS_Q10 (AR9_SW + 0x034)
|
||||
#define AR9_SW_P0_ECW_Q32 (AR9_SW + 0x038)
|
||||
#define AR9_SW_P0_ECW_Q10 (AR9_SW + 0x03C)
|
||||
#define AR9_SW_P1_ECS_Q32 (AR9_SW + 0x040)
|
||||
#define AR9_SW_P1_ECS_Q10 (AR9_SW + 0x044)
|
||||
#define AR9_SW_P1_ECW_Q32 (AR9_SW + 0x048)
|
||||
#define AR9_SW_P1_ECW_Q10 (AR9_SW + 0x04C)
|
||||
#define AR9_SW_P2_ECS_Q32 (AR9_SW + 0x050)
|
||||
#define AR9_SW_P2_ECS_Q10 (AR9_SW + 0x054)
|
||||
#define AR9_SW_P2_ECW_Q32 (AR9_SW + 0x058)
|
||||
#define AR9_SW_P2_ECW_Q10 (AR9_SW + 0x05C)
|
||||
#define AR9_SW_INT_ENA (AR9_SW + 0x060)
|
||||
#define AR9_SW_INT_ST (AR9_SW + 0x064)
|
||||
#define AR9_SW_GCTL0 (AR9_SW + 0x068)
|
||||
#define AR9_SW_GCTL1 (AR9_SW + 0x06C)
|
||||
#define AR9_SW_ARP (AR9_SW + 0x070)
|
||||
#define AR9_SW_STRM_CTL (AR9_SW + 0x074)
|
||||
#define AR9_SW_RGMII_CTL (AR9_SW + 0x078)
|
||||
#define AR9_SW_1P_PRT (AR9_SW + 0x07C)
|
||||
#define AR9_SW_GBKT_SZBS (AR9_SW + 0x080)
|
||||
#define AR9_SW_GBKT_SZEBS (AR9_SW + 0x084)
|
||||
#define AR9_SW_BF_TH (AR9_SW + 0x088)
|
||||
#define AR9_SW_PMAC_HD_CTL (AR9_SW + 0x08C)
|
||||
#define AR9_SW_PMAC_SA1 (AR9_SW + 0x090)
|
||||
#define AR9_SW_PMAC_SA2 (AR9_SW + 0x094)
|
||||
#define AR9_SW_PMAC_DA1 (AR9_SW + 0x098)
|
||||
#define AR9_SW_PMAC_DA2 (AR9_SW + 0x09C)
|
||||
#define AR9_SW_PMAC_VLAN (AR9_SW + 0x0A0)
|
||||
#define AR9_SW_PMAC_TX_IPG (AR9_SW + 0x0A4)
|
||||
#define AR9_SW_PMAC_RX_IPG (AR9_SW + 0x0A8)
|
||||
#define AR9_SW_ADR_TB_CTL0 (AR9_SW + 0x0AC)
|
||||
#define AR9_SW_ADR_TB_CTL1 (AR9_SW + 0x0B0)
|
||||
#define AR9_SW_ADR_TB_CTL2 (AR9_SW + 0x0B4)
|
||||
#define AR9_SW_ADR_TB_ST0 (AR9_SW + 0x0B8)
|
||||
#define AR9_SW_ADR_TB_ST1 (AR9_SW + 0x0BC)
|
||||
#define AR9_SW_ADR_TB_ST2 (AR9_SW + 0x0C0)
|
||||
#define AR9_SW_RMON_CTL (AR9_SW + 0x0C4)
|
||||
#define AR9_SW_RMON_ST (AR9_SW + 0x0C8)
|
||||
#define AR9_SW_MDIO_CTL (AR9_SW + 0x0CC)
|
||||
#define AR9_SW_MDIO_DATA (AR9_SW + 0x0D0)
|
||||
#define AR9_SW_TP_FLT_ACT (AR9_SW + 0x0D4)
|
||||
#define AR9_SW_PRTCL_FLT_ACT (AR9_SW + 0x0D8)
|
||||
#define AR9_SW_VLAN_FLT0 (AR9_SW + 0x100)
|
||||
#define AR9_SW_VLAN_FLT1 (AR9_SW + 0x104)
|
||||
#define AR9_SW_VLAN_FLT2 (AR9_SW + 0x108)
|
||||
#define AR9_SW_VLAN_FLT3 (AR9_SW + 0x10C)
|
||||
#define AR9_SW_VLAN_FLT4 (AR9_SW + 0x110)
|
||||
#define AR9_SW_VLAN_FLT5 (AR9_SW + 0x114)
|
||||
#define AR9_SW_VLAN_FLT6 (AR9_SW + 0x118)
|
||||
#define AR9_SW_VLAN_FLT7 (AR9_SW + 0x11C)
|
||||
#define AR9_SW_VLAN_FLT8 (AR9_SW + 0x120)
|
||||
#define AR9_SW_VLAN_FLT9 (AR9_SW + 0x124)
|
||||
#define AR9_SW_VLAN_FLT10 (AR9_SW + 0x128)
|
||||
#define AR9_SW_VLAN_FLT11 (AR9_SW + 0x12C)
|
||||
#define AR9_SW_VLAN_FLT12 (AR9_SW + 0x130)
|
||||
#define AR9_SW_VLAN_FLT13 (AR9_SW + 0x134)
|
||||
#define AR9_SW_VLAN_FLT14 (AR9_SW + 0x138)
|
||||
#define AR9_SW_VLAN_FLT15 (AR9_SW + 0x13C)
|
||||
#define AR9_SW_TP_FLT10 (AR9_SW + 0x140)
|
||||
#define AR9_SW_TP_FLT32 (AR9_SW + 0x144)
|
||||
#define AR9_SW_TP_FLT54 (AR9_SW + 0x148)
|
||||
#define AR9_SW_TP_FLT76 (AR9_SW + 0x14C)
|
||||
#define AR9_SW_DFSRV_MAP0 (AR9_SW + 0x150)
|
||||
#define AR9_SW_DFSRV_MAP1 (AR9_SW + 0x154)
|
||||
#define AR9_SW_DFSRV_MAP2 (AR9_SW + 0x158)
|
||||
#define AR9_SW_DFSRV_MAP3 (AR9_SW + 0x15C)
|
||||
#define AR9_SW_TCP_PF0 (AR9_SW + 0x160)
|
||||
#define AR9_SW_TCP_PF1 (AR9_SW + 0x164)
|
||||
#define AR9_SW_TCP_PF2 (AR9_SW + 0x168)
|
||||
#define AR9_SW_TCP_PF3 (AR9_SW + 0x16C)
|
||||
#define AR9_SW_TCP_PF4 (AR9_SW + 0x170)
|
||||
#define AR9_SW_TCP_PF5 (AR9_SW + 0x174)
|
||||
#define AR9_SW_TCP_PF6 (AR9_SW + 0x178)
|
||||
#define AR9_SW_TCP_PF7 (AR9_SW + 0x17C)
|
||||
#define AR9_SW_RA_03_00 (AR9_SW + 0x180)
|
||||
#define AR9_SW_RA_07_04 (AR9_SW + 0x184)
|
||||
#define AR9_SW_RA_0B_08 (AR9_SW + 0x188)
|
||||
#define AR9_SW_RA_0F_0C (AR9_SW + 0x18C)
|
||||
#define AR9_SW_RA_13_10 (AR9_SW + 0x190)
|
||||
#define AR9_SW_RA_17_14 (AR9_SW + 0x194)
|
||||
#define AR9_SW_RA_1B_18 (AR9_SW + 0x198)
|
||||
#define AR9_SW_RA_1F_1C (AR9_SW + 0x19C)
|
||||
#define AR9_SW_RA_23_20 (AR9_SW + 0x1A0)
|
||||
#define AR9_SW_RA_27_24 (AR9_SW + 0x1A4)
|
||||
#define AR9_SW_RA_2B_28 (AR9_SW + 0x1A8)
|
||||
#define AR9_SW_RA_2F_2C (AR9_SW + 0x1AC)
|
||||
#define AR9_SW_F0 (AR9_SW + 0x1B0)
|
||||
#define AR9_SW_F1 (AR9_SW + 0x1B4)
|
||||
|
||||
#define REG32(addr) *((volatile u32 *)(addr))
|
||||
@ -0,0 +1,104 @@
|
||||
/*
|
||||
* (C) Copyright 2003-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains the configuration parameters for the Danube reference board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* #define DEBUG */
|
||||
|
||||
#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */
|
||||
#define CONFIG_MIPS34KC 1 /* MIPS 34Kc CPU core */
|
||||
#define CONFIG_AR9 1 /* an AR9 device */
|
||||
#define CONFIG_EASY50812 1 /* on the AR9 reference board */
|
||||
#define CONFIG_SYS_MAX_RAM 32*1024*1024 /* 32 MB */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* using CFI flash driver */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
|
||||
|
||||
/* use PPL1 and fixed values for CPU / DDR and bus speed */
|
||||
#define CONFIG_USE_PLL1
|
||||
#define CONFIG_CPU_333M_RAM_166M
|
||||
#define CONFIG_CLASS_II_DDR_PAD
|
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* no cache */
|
||||
#else
|
||||
#define CONFIG_SYS_EBU_BOOT
|
||||
#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */
|
||||
#endif
|
||||
|
||||
#ifndef CPU_CLOCK_RATE
|
||||
#define CPU_CLOCK_RATE (ifx_get_cpuclk())
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_PROMPT "AR9 => " /* Monitor Command Prompt */
|
||||
#undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
|
||||
|
||||
/*
|
||||
* Include common defines/options for all Lantiq boards
|
||||
*/
|
||||
#include "ifx-common.h"
|
||||
|
||||
/*
|
||||
* Cache Configuration (cpu/chip specific, ar9)
|
||||
*/
|
||||
#define CONFIG_SYS_DCACHE_SIZE (16384)
|
||||
#define CONFIG_SYS_ICACHE_SIZE (16384)
|
||||
#define CONFIG_SYS_CACHELINE_SIZE (32)
|
||||
#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#if 0
|
||||
#define CONFIG_M4530_ETH
|
||||
#define CONFIG_M4530_FPGA
|
||||
#endif
|
||||
|
||||
#define CONFIG_IFX_ETOP /* lantiq ethernet cpe interface */
|
||||
#define CLK_OUT2_25MHZ
|
||||
#define CONFIG_EXTRA_SWITCH /* search for external switches like tantos */
|
||||
#define CONFIG_RMII /* use interface in RMII mode */
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_CMD_MII /* enable MII command */
|
||||
|
||||
#define CONFIG_IFX_ASC /* use lantiq ASC driver */
|
||||
#ifdef CONFIG_USE_ASC0
|
||||
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100400
|
||||
#else
|
||||
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
/* Configuration of EBU: */
|
||||
/* starting address from 0xb0000000 */
|
||||
/* make the flash available from RAM boot */
|
||||
# define CONFIG_EBU_ADDSEL0 0x10000031
|
||||
# define CONFIG_EBU_BUSCON0 0x0001D7FF
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue