kernel: bump 5.4 to 5.4.51
update via update_kernel.sh -v -u 5.4 Removed upstreamed patches: 350-MIPS-Add-missing-EHB-in-mtc0-mfc0-sequence-for-DSPen.patch Script refreshed patches: 902-debloat_proc.patch 904-debloat_dma_buf.patch Attempted merge conflict in following patches: 0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch Build system: x86_64 Build tested: ipq806x (Netgear R7800) Signed-off-by: John Audia <graysky@archlinux.us> [fixed sha256sum of the tarball] Signed-off-by: Petr Štetiar <ynezz@true.cz>master
John Audia
4 years ago
committed by
Petr Štetiar
parent
f93267bccf
commit
039fd27173
@ -1,61 +0,0 @@
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From db4603e30effd74d4adb6bcdf73072b2c06fafcd Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Fri, 3 Jul 2020 00:07:15 +0200
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Subject: [PATCH] MIPS: Add missing EHB in mtc0 -> mfc0 sequence for DSPen
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This resolves the hazard between the mtc0 in the change_c0_status() and
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the mfc0 in configure_exception_vector(). Without resolving this hazard
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configure_exception_vector() could read an old value and would restore
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this old value again. This would revert the changes change_c0_status()
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did. I checked this by printing out the read_c0_status() at the end of
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per_cpu_trap_init() and the ST0_MX is not set without this patch.
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The hazard is documented in the MIPS Architecture Reference Manual Vol.
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III: MIPS32/microMIPS32 Privileged Resource Architecture (MD00088), rev
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6.03 table 8.1 which includes:
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Producer | Consumer | Hazard
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----------|----------|----------------------------
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mtc0 | mfc0 | any coprocessor 0 register
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I saw this hazard on an Atheros AR9344 rev 2 SoC with a MIPS 74Kc CPU.
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There the change_c0_status() function would activate the DSPen by
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setting ST0_MX in the c0_status register. This was reverted and then the
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system got a DSP exception when the DSP registers were saved in
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save_dsp() in the first process switch. The crash looks like this:
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[ 0.089999] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
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[ 0.097796] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
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[ 0.107070] Kernel panic - not syncing: Unexpected DSP exception
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[ 0.113470] Rebooting in 1 seconds..
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We saw this problem in OpenWrt only on the MIPS 74Kc based Atheros SoCs,
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not on the 24Kc based SoCs. We only saw it with kernel 5.4 not with
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kernel 4.19, in addition we had to use GCC 8.4 or 9.X, with GCC 8.3 it
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did not happen.
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In the kernel I bisected this problem to commit 9012d011660e ("compiler:
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allow all arches to enable CONFIG_OPTIMIZE_INLINING"), but when this was
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reverted it also happened after commit 172dcd935c34b ("MIPS: Always
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allocate exception vector for MIPSr2+").
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Commit 0b24cae4d535 ("MIPS: Add missing EHB in mtc0 -> mfc0 sequence.")
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does similar changes to a different file. I am not sure if there are
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more places affected by this problem.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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Cc: <stable@vger.kernel.org>
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---
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arch/mips/kernel/traps.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/mips/kernel/traps.c
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+++ b/arch/mips/kernel/traps.c
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@@ -2126,6 +2126,7 @@ static void configure_status(void)
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change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
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status_set);
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+ back_to_back_c0_hazard();
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}
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unsigned int hwrena;
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