ar71xx: Fix potentially missed IRQ handling during dispatch

If both interrupts are set in the current implementation
only the 1st will be handled and the 2nd will be skipped
due to the "if else" condition.

Fix this by using the same approach as done for QCA955x
just below it.

Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
master
Koen Vandeputte 5 years ago
parent 78c3a18a1e
commit 00d48bcac0

@ -0,0 +1,57 @@
From 3fe7841bf5a582dc7fd198e5bf70162ea418a22a Mon Sep 17 00:00:00 2001
From: Koen Vandeputte <koen.vandeputte@ncentric.com>
Date: Wed, 11 Sep 2019 11:02:19 +0200
Subject: [PATCH] MIPS: ath79: Fix potentially missed IRQ handling during
dispatch
If both interrupts are set in the current implementation
only the 1st will be handled and the 2nd will be skipped
due to the "if else" condition.
Fix this by using the same approach as done for QCA955x
just below it.
Fixes: fce5cc6e0ddc ("MIPS: ath79: add IRQ handling code for AR934X")
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
CC: Felix Fietkau <nbd@nbd.name>
CC: Gabor Juhos <juhosg@freemail.hu>
CC: James Hogan <jhogan@kernel.org>
CC: Paul Burton <paul.burton@mips.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: stable@vger.kernel.org # v3.2+
---
arch/mips/ath79/irq.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 2dfff1f19004..a03a6bcaf6fd 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -32,15 +32,21 @@ static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
u32 status;
status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
+ status &= AR934X_PCIE_WMAC_INT_PCIE_ALL | AR934X_PCIE_WMAC_INT_WMAC_ALL;
+
+ if (status == 0) {
+ spurious_interrupt();
+ return;
+ }
if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
ath79_ddr_wb_flush(3);
generic_handle_irq(ATH79_IP2_IRQ(0));
- } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
+ }
+
+ if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
ath79_ddr_wb_flush(4);
generic_handle_irq(ATH79_IP2_IRQ(1));
- } else {
- spurious_interrupt();
}
}
--
2.17.1

@ -0,0 +1,57 @@
From 3fe7841bf5a582dc7fd198e5bf70162ea418a22a Mon Sep 17 00:00:00 2001
From: Koen Vandeputte <koen.vandeputte@ncentric.com>
Date: Wed, 11 Sep 2019 11:02:19 +0200
Subject: [PATCH] MIPS: ath79: Fix potentially missed IRQ handling during
dispatch
If both interrupts are set in the current implementation
only the 1st will be handled and the 2nd will be skipped
due to the "if else" condition.
Fix this by using the same approach as done for QCA955x
just below it.
Fixes: fce5cc6e0ddc ("MIPS: ath79: add IRQ handling code for AR934X")
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
CC: Felix Fietkau <nbd@nbd.name>
CC: Gabor Juhos <juhosg@freemail.hu>
CC: James Hogan <jhogan@kernel.org>
CC: Paul Burton <paul.burton@mips.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: stable@vger.kernel.org # v3.2+
---
arch/mips/ath79/irq.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 2dfff1f19004..a03a6bcaf6fd 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -32,15 +32,21 @@ static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
u32 status;
status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
+ status &= AR934X_PCIE_WMAC_INT_PCIE_ALL | AR934X_PCIE_WMAC_INT_WMAC_ALL;
+
+ if (status == 0) {
+ spurious_interrupt();
+ return;
+ }
if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
ath79_ddr_wb_flush(3);
generic_handle_irq(ATH79_IP2_IRQ(0));
- } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
+ }
+
+ if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
ath79_ddr_wb_flush(4);
generic_handle_irq(ATH79_IP2_IRQ(1));
- } else {
- spurious_interrupt();
}
}
--
2.17.1
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