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144 lines
4.8 KiB
Diff
144 lines
4.8 KiB
Diff
5 years ago
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From a4296994eb8061ee3455721a296c387c639bf635 Mon Sep 17 00:00:00 2001
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From: Bernd Edlinger <bernd.edlinger@hotmail.de>
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Date: Tue, 15 Jan 2019 14:01:29 +0000
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Subject: [PATCH 13/28] rt2x00: Work around a firmware bug with shared keys
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Apparently the rt2x61 firmware fails temporarily to decode
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broadcast packets if the shared keys are not assigned
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in the "correct" sequence. At the same time unicast
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packets work fine, since they are encrypted with the
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pairwise key.
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At least with WPA2 CCMP mode the shared keys are
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set in the following sequence: keyidx=1, 2, 1, 2.
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After a while only keyidx 2 gets decrypted, and
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keyidx 1 is ignored, probably because there is never
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a keyidx 3.
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Symptoms are arping -b works for 10 minutes, since
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keyidx=2 is used for broadcast, and then it stops
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working for 10 minutes, because keyidx=1 is used.
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That failure mode repeats forever.
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Note, the firmware does not even know which keyidx
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corresponds to which hw_key_idx so the firmware is
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trying to be smarter than the driver, which is bound
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to fail.
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As workaround the function rt61pci_config_shared_key
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requests software decryption of the shared keys,
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by returning EOPNOTSUPP. However, pairwise keys are
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still handled by hardware which works just fine.
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Signed-off-by: Bernd Edlinger <bernd.edlinger@hotmail.de>
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Acked-by: Stanislaw Gruszka <sgruszka@redhat.com>
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Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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---
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drivers/net/wireless/ralink/rt2x00/rt61pci.c | 93 +-------------------
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1 file changed, 4 insertions(+), 89 deletions(-)
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--- a/drivers/net/wireless/ralink/rt2x00/rt61pci.c
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+++ b/drivers/net/wireless/ralink/rt2x00/rt61pci.c
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@@ -321,97 +321,12 @@ static int rt61pci_config_shared_key(str
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struct rt2x00lib_crypto *crypto,
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struct ieee80211_key_conf *key)
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{
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- struct hw_key_entry key_entry;
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- struct rt2x00_field32 field;
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- u32 mask;
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- u32 reg;
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-
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- if (crypto->cmd == SET_KEY) {
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- /*
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- * rt2x00lib can't determine the correct free
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- * key_idx for shared keys. We have 1 register
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- * with key valid bits. The goal is simple, read
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- * the register, if that is full we have no slots
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- * left.
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- * Note that each BSS is allowed to have up to 4
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- * shared keys, so put a mask over the allowed
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- * entries.
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- */
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- mask = (0xf << crypto->bssidx);
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-
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- reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR0);
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- reg &= mask;
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-
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- if (reg && reg == mask)
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- return -ENOSPC;
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-
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- key->hw_key_idx += reg ? ffz(reg) : 0;
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-
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- /*
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- * Upload key to hardware
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- */
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- memcpy(key_entry.key, crypto->key,
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- sizeof(key_entry.key));
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- memcpy(key_entry.tx_mic, crypto->tx_mic,
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- sizeof(key_entry.tx_mic));
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- memcpy(key_entry.rx_mic, crypto->rx_mic,
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- sizeof(key_entry.rx_mic));
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-
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- reg = SHARED_KEY_ENTRY(key->hw_key_idx);
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- rt2x00mmio_register_multiwrite(rt2x00dev, reg,
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- &key_entry, sizeof(key_entry));
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-
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- /*
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- * The cipher types are stored over 2 registers.
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- * bssidx 0 and 1 keys are stored in SEC_CSR1 and
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- * bssidx 1 and 2 keys are stored in SEC_CSR5.
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- * Using the correct defines correctly will cause overhead,
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- * so just calculate the correct offset.
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- */
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- if (key->hw_key_idx < 8) {
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- field.bit_offset = (3 * key->hw_key_idx);
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- field.bit_mask = 0x7 << field.bit_offset;
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-
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- reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR1);
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- rt2x00_set_field32(®, field, crypto->cipher);
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- rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg);
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- } else {
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- field.bit_offset = (3 * (key->hw_key_idx - 8));
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- field.bit_mask = 0x7 << field.bit_offset;
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-
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- reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR5);
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- rt2x00_set_field32(®, field, crypto->cipher);
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- rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg);
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- }
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-
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- /*
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- * The driver does not support the IV/EIV generation
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- * in hardware. However it doesn't support the IV/EIV
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- * inside the ieee80211 frame either, but requires it
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- * to be provided separately for the descriptor.
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- * rt2x00lib will cut the IV/EIV data out of all frames
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- * given to us by mac80211, but we must tell mac80211
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- * to generate the IV/EIV data.
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- */
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- key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
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- }
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-
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/*
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- * SEC_CSR0 contains only single-bit fields to indicate
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- * a particular key is valid. Because using the FIELD32()
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- * defines directly will cause a lot of overhead, we use
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- * a calculation to determine the correct bit directly.
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+ * Let the software handle the shared keys,
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+ * since the hardware decryption does not work reliably,
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+ * because the firmware does not know the key's keyidx.
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*/
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- mask = 1 << key->hw_key_idx;
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-
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- reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR0);
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- if (crypto->cmd == SET_KEY)
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- reg |= mask;
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- else if (crypto->cmd == DISABLE_KEY)
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- reg &= ~mask;
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- rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg);
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-
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- return 0;
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+ return -EOPNOTSUPP;
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}
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static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
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