You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
64 lines
2.8 KiB
Diff
64 lines
2.8 KiB
Diff
6 years ago
|
From patchwork Thu Sep 28 12:58:37 2017
|
||
|
|
Content-Type: text/plain; charset="utf-8"
|
||
|
|
MIME-Version: 1.0
|
||
|
|
Content-Transfer-Encoding: 7bit
|
||
|
|
Subject: [v2,6/7] PCI: aardvark: fix PCIe max read request size setting
|
||
|
|
X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||
|
|
X-Patchwork-Id: 819591
|
||
|
|
Message-Id: <20170928125838.11887-7-thomas.petazzoni@free-electrons.com>
|
||
|
|
To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
|
||
|
|
Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
|
||
|
|
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
|
||
|
|
<gregory.clement@free-electrons.com>,
|
||
|
|
Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
|
||
|
|
Yehuda Yitschak <yehuday@marvell.com>,
|
||
|
|
linux-arm-kernel@lists.infradead.org, Antoine Tenart
|
||
|
|
<antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
|
||
|
|
<miquel.raynal@free-electrons.com>, Evan Wang <xswang@marvell.com>,
|
||
|
|
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||
|
|
Date: Thu, 28 Sep 2017 14:58:37 +0200
|
||
|
|
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||
|
|
List-Id: <linux-pci.vger.kernel.org>
|
||
|
|
|
||
|
|
From: Evan Wang <xswang@marvell.com>
|
||
|
|
|
||
|
|
There is an obvious typo issue in the definition of the PCIe maximum
|
||
|
|
read request size: a bit shift is directly used as a value, while it
|
||
|
|
should be used to shift the correct value.
|
||
|
|
|
||
|
|
This is part of fixing bug
|
||
|
|
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
|
||
|
|
reported as the user to be important to get a Intel 7260 mini-PCIe
|
||
|
|
WiFi card working.
|
||
|
|
|
||
|
|
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
|
||
|
|
Signed-off-by: Evan Wang <xswang@marvell.com>
|
||
|
|
Reviewed-by: Victor Gu <xigu@marvell.com>
|
||
|
|
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
|
||
|
|
[Thomas: tweak commit log.]
|
||
|
|
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||
|
|
---
|
||
|
|
drivers/pci/host/pci-aardvark.c | 4 +++-
|
||
|
|
1 file changed, 3 insertions(+), 1 deletion(-)
|
||
|
|
|
||
|
|
--- a/drivers/pci/host/pci-aardvark.c
|
||
|
|
+++ b/drivers/pci/host/pci-aardvark.c
|
||
|
|
@@ -33,6 +33,7 @@
|
||
|
|
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
|
||
|
|
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
|
||
|
|
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
|
||
|
|
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
|
||
|
|
#define PCIE_CORE_MPS_UNIT_BYTE 128
|
||
|
|
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
|
||
|
|
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
|
||
|
|
@@ -303,7 +304,8 @@ static void advk_pcie_setup_hw(struct ad
|
||
|
|
(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
|
||
|
|
PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
|
||
|
|
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
|
||
|
|
- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
|
||
|
|
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
|
||
|
|
+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
|
||
|
|
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
|
||
|
|
|
||
|
|
/* Program PCIe Control 2 to disable strict ordering */
|