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openwrt/target/linux/apm821xx/dts/apollo3g.dtsi

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apm821xx: add support for the Western Digital MyBook Live Series Hardware Highlights: This patch adds support for Western Digital MyBook Live Series: CPU: AMCC PowerPC UNKNOWN (PVR=12c41c83) at 800 MHz (PLB=200, OPB=100, EBC=100 MHz) 32 kB I-Cache 32 kB D-Cache, 256 kB L2-Cache, 32 kB OnChip Memory Board: Apollo-3G - APM82181 Board, 1*SATA DRAM: 256 MB (2x NT5TU64M16GG-AC) FLASH: 512 kB (SST 39VF040) Ethernet: 1xRGMII - 1 Gbit - Broadcom PHY BCM54610 WARNING: The serial port needs a TTL/RS-232 v3.3 level converter! The MyBook Live Duo additionally features a 1x USB 2.0 host port and can support a second hard-drive. This target produces two images for a target. 1. ext4 image The extracted/raw image can be directly installed on the internal HDD via "dd if=img.ext4 of=/dev/sdX". This can either be done in place with the stock MyBook Live firmware via ssh. Or by removing the HDD and writing the image with a different PC. The the compressed images are useful for sysupgrade. 2. recovery.tar image for TFTP and Serial. extract the recovery.tar to a TFTP server directory. On the MyBook Live (Duo) serial port - Hit Enter during u-boot and insert: # setenv serverip 192.168.1.254; setenv ipaddr 192.168.1.1; run net_self Where 192.168.1.254 is your TFTP server. Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
8 years ago
/*
* Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
* (c) Copyright 2010 Western Digital Technologies, Inc. All Rights Reserved.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/ {
#address-cells = <2>;
#size-cells = <1>;
compatible = "amcc,apollo3g";
dcr-parent = <&{/cpus/cpu@0}>;
aliases {
ethernet0 = &EMAC0;
serial0 = &UART0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "PowerPC,apm82181";
reg = <0x00000000>;
clock-frequency = <0>; /* Filled in by U-Boot */
timebase-frequency = <0>; /* Filled in by U-Boot */
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
next-level-cache = <&L2C0>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
};
UIC0: interrupt-controller0 {
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0x0c0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
UIC1: interrupt-controller1 {
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <1>;
dcr-reg = <0x0d0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
interrupt-parent = <&UIC0>;
};
UIC2: interrupt-controller2 {
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <2>;
dcr-reg = <0x0e0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
interrupt-parent = <&UIC0>;
};
UIC3: interrupt-controller3 {
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <3>;
dcr-reg = <0x0f0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
interrupt-parent = <&UIC0>;
};
OCM1: ocm@400040000 {
compatible = "ibm,ocm";
status = "okay";
cell-index = <1>;
/* configured in U-Boot */
reg = <4 0x00040000 0x8000>; /* 32K */
};
SDR0: sdr {
compatible = "ibm,sdr-460ex";
dcr-reg = <0x00e 0x002>;
};
CPR0: cpr {
compatible = "ibm,cpr-460ex";
dcr-reg = <0x00c 0x002>;
};
CPM0: cpm {
compatible = "ibm,cpm";
dcr-access-method = "native";
dcr-reg = <0x160 0x003>;
unused-units = <0x00000100>;
idle-doze = <0x02000000>;
standby = <0xfeff791d>;
};
L2C0: l2c {
compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
dcr-reg = <0x020 0x008
0x030 0x008>;
cache-line-size = <32>;
cache-size = <262144>;
interrupt-parent = <&UIC1>;
interrupts = <11 1>;
};
plb {
compatible = "ibm,plb-460ex", "ibm,plb4";
#address-cells = <2>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; /* Filled in by U-Boot */
SDRAM0: sdram {
compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
dcr-reg = <0x010 0x002>;
};
CRYPTO: crypto@180000 {
compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
reg = <4 0x00180000 0x80400>;
interrupt-parent = <&UIC0>;
interrupts = <0x1d 0x4>;
};
PKA: pka@114000 {
device_type = "pka";
compatible = "ppc4xx-pka", "amcc,ppc4xx-pka";
reg = <0 0x00114000 0x4000>;
interrupt-parent = <&UIC0>;
interrupts = <0x14 0x2>;
};
HWRNG: trng@110000 {
compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
reg = <4 0x00110000 0x50>;
};
MAL0: mcmal {
compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
descriptor-memory = "ocm";
dcr-reg = <0x180 0x062>;
num-tx-chans = <1>;
num-rx-chans = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-parent = <&UIC2>;
interrupts = < /*TXEOB*/ 0x6 0x4
/*RXEOB*/ 0x7 0x4
/*SERR*/ 0x3 0x4
/*TXDE*/ 0x4 0x4
/*RXDE*/ 0x5 0x4
/*TX0 COAL*/ 0x8 0x2
/*TX1 COAL 0x9 0x2*/
/*RX0 COAL*/ 0xc 0x2
/*RX1 COAL 0xd 0x2*/ >;
};
AHBDMA: dma@bffd0800 {
compatible = "snps,dma-spear1340";
reg = <4 0xbffd0800 0x400>;
interrupt-parent = <&UIC0>;
interrupts = <25 4>;
#dma-cells = <3>;
/* use autoconfiguration for the dma setup */
};
SATA0: sata@bffd1000 {
compatible = "amcc,sata-460ex";
reg = <4 0xbffd1000 0x800>;
interrupt-parent = <&UIC0>;
interrupts = <26 4>;
dmas = <&AHBDMA 0 0 1>;
dma-names = "sata-dma";
};
SATA1: sata@bffd1800 {
compatible = "amcc,sata-460ex";
reg = <4 0xbffd1800 0x800>;
interrupt-parent = <&UIC0>;
interrupts = <27 4>;
dmas = <&AHBDMA 1 0 2>;
dma-names = "sata-dma";
};
USBOTG0: usbotg@bff80000 {
compatible = "snps,dwc2";
reg = <4 0xbff80000 0x10000>;
interrupt-parent = <&USBOTG0>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </* USB-OTG */ 0 &UIC2 0x1c 4
/* HIGH-POWER */ 1 &UIC1 0x1a 8
/* DMA */ 2 &UIC0 0xc 4>;
dr_mode = "host";
};
POB0: opb {
compatible = "ibm,opb-460ex", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xb0000000 0x4 0xb0000000 0x50000000>;
clock-frequency = <0>; /* Filled in by U-Boot */
EBC0: ebc {
compatible = "ibm,ebc-460ex", "ibm,ebc";
dcr-reg = <0x012 0x002>;
#address-cells = <2>;
#size-cells = <1>;
clock-frequency = <0>; /* Filled in by U-Boot */
interrupts = <0x6 0x4>;
interrupt-parent = <&UIC1>;
/* ranges property are supplied by U-Boot */
ranges = <0x0 0x0 0xfff80000 0x00080000
0x1 0x0 0x00000000 0x00000000
0x2 0x0 0x00000000 0x00000000>;
/* Define device tree for Apollo3g NAS NOR flash
* The NOR doesn't work when "enable-button" GPIO
* is asserted.
*/
nor_flash@0,0 {
compatible = "amd,s29gl512n", "jedec-probe", "cfi-flash", "mtd-rom";
bank-width = <1>;
reg = <0x00000000 0x00000000 0x00080000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
/* Part of bootrom - Don't use it without a jump */
label = "free";
reg = <0x00000000 0x0001e000>;
};
partition@1 {
label = "env";
reg = <0x0001e000 0x00002000>;
};
partition@2 {
label = "uboot";
reg = <0x00020000 0x00050000>;
};
};
ndfc@1,0 {
compatible = "ibm,ndfc";
reg = <0x00000001 0x00000000 0x00002000>;
ccr = <0x00001000>;
bank-settings = <0x80002222>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
nand {
#address-cells = <1>;
#size-cells = <1>;
};
};
};
gpio0: gpio0@e0000000 {
compatible = "wd,mbl-gpio", "ti,74273";
reg-names = "dat";
reg = <0xe0000000 0x1>;
#gpio-cells = <2>;
gpio-controller;
enable-phy {
/* toggle to reset EMAC PHY */
gpio-hog;
line-name = "enable EMAC PHY";
gpios = <0 1>;
output-low;
};
enable-button {
/* Defined in u-boot as: NOT_NOR
* "enables features other than NOR
* specifically, the buffer at CS2"
* (button).
*
* Note: This option is disabled as
* it prevents the system from being
* rebooted successfully.
*/
gpio-hog;
line-name = "Enable Reset Button, disable NOR";
gpios = <1 0>;
output-low;
};
enable-usb {
gpio-hog;
line-name = "Power USB Core";
gpios = <2 1>;
output-low;
};
enable-port1 {
gpio-hog;
line-name = "Power Drive Port 1";
gpios = <3 1>;
output-low;
};
enable-port0 {
gpio-hog;
line-name = "Power Drive Port 0";
gpios = <7 1>;
output-low;
};
};
gpio1: gpio1@e0100000 {
compatible = "wd,mbl-gpio", "ti,74244";
reg-names = "dat";
reg = <0xe0100000 0x1>;
#gpio-cells = <2>;
gpio-controller;
no-output;
};
UART0: serial@ef600300 {
device_type = "serial";
compatible = "ns16550";
reg = <0xef600300 0x00000008>;
virtual-reg = <0xef600300>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
interrupts = <0x1 0x4>;
};
gpio-leds {
compatible = "gpio-leds";
power-red {
label = "mbl:red:power";
gpios = <&gpio0 4 0>;
linux,default-trigger = "panic";
};
power-green {
label = "mbl:green:power";
gpios = <&gpio0 5 0>;
linux,default-trigger = "default-on";
};
power-blue {
label = "mbl:blue:power";
gpios = <&gpio0 6 0>;
linux,default-trigger = "cpu0";
};
};
gpio_keys_polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <60>; /* 3 * 20 = 60ms */
autorepeat;
button@1 {
label = "Reset button";
linux,code = <0x198>; /* KEY_RESTART */
gpios = <&gpio1 2 1>;
};
};
RGMII0: emac-rgmii@ef601500 {
compatible = "ibm,rgmii-405ex", "ibm,rgmii";
reg = <0xef601500 0x00000008>;
has-mdio;
};
TAH0: emac-tah@ef601350 {
compatible = "ibm,tah-460ex", "ibm,tah";
reg = <0xef601350 0x00000030>;
};
EMAC0: ethernet@ef600c00 {
device_type = "network";
compatible = "ibm,emac-405ex", "ibm,emac4sync";
interrupt-parent = <&EMAC0>;
interrupts = <0x0 0x1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
reg = <0xef600c00 0x000000c4>;
local-mac-address = [000000000000]; /* Filled in by U-Boot */
mal-device = <&MAL0>;
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
max-frame-size = <9000>;
rx-fifo-size = <16384>;
tx-fifo-size = <2048>;
phy-mode = "rgmii";
phy-map = <0x00000000>;
rgmii-device = <&RGMII0>;
rgmii-channel = <0>;
tah-device = <&TAH0>;
tah-channel = <0>;
has-inverted-stacr-oc;
has-new-stacr-staopc;
};
};
ADMA: adma {
compatible = "amcc,apm82181-adma";
device_type = "dma";
#address-cells = <2>;
#size-cells = <1>;
dma-4channel@1 {
compatible = "amcc,apm82181-dma-4channel";
cell-index = <1>;
label = "plb_dma1";
interrupt-parent = <&UIC0>;
interrupts = <0xd 0x4>;
pool_size = <0x4000>;
dcr-reg = <0x208 0x20f>;
};
dma-4channel@2 {
compatible = "amcc,apm82181-dma-4channel";
cell-index = <2>;
label = "plb_dma2";
interrupt-parent = <&UIC0>;
interrupts = <0xe 0x4>;
pool_size = <0x4000>;
dcr-reg = <0x210 0x217>;
};
dma-4channel@3 {
compatible = "amcc,apm82181-dma-4channel";
cell-index = <3>;
label = "plb_dma3";
interrupt-parent = <&UIC0>;
interrupts = <0xf 0x4>;
pool_size = <0x4000>;
dcr-reg = <0x218 0x21f>;
};
};
DMA: plb_dma@400300200 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "amcc,dma";
cell-index = <0>;
reg = <4 00300200 200>;
dcr-reg = <0x100 0x13f>;
interrupt-parent = <&UIC0>;
interrupts = <0>;
interrupt-map = < /* chan0 */ 0 &UIC0 12 4>;
dma-4channel@0{
compatible = "amcc,dma-4channel";
cell-index = <0>;
label = "channel0";
reg = <0x100 0x107>;
};
};
};
};